TCI6630K2L Datasheet, PDF (203/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Table 9-58. ARM Endian Configuration Register 2
Default Values
ARM ENDIAN CONFIGURATION REGISTER 2
ARMENDIAN_CFG0_2
ARMENDIAN_CFG1_2
ARMENDIAN_CFG2_2
ARMENDIAN_CFG3_2
ARMENDIAN_CFG4_2
ARMENDIAN_CFG5_2
ARMENDIAN_CFG6_2
ARMENDIAN_CFG7_2
DEFAULT
VALUES
0x00000001
0x00000001
0x00000001
0x00000001
0x00000001
0x00000001
0x00000001
0x00000001
Bit
31-1
0
Field
Reserved
DIS
Table 9-59. ARM Endian Configuration Register 2 Field Descriptions
Description
Reserved
Disabling the word swap of a region
• 0 : Enable word swap for region
• 1 : Disable word swap for region
9.2.3.28 Chip Miscellaneous Control (CHIP_MISC_CTL0) Register
Figure 9-45. Chip Miscellaneous Control Register (CHIP_MISC_CTL0)
31
19
18
Reserved
USB_PME_EN
R-0
RW-0
16
13
12
Reserved
MSMC_BLOCK_PARITY_RST
R-0
RW-0
Legend: R = Read only; W = Write only; -n = value after reset
11
3
Reserved
RW-0
17
Reserved
R-0
2
0
QM_PRIORITY
RW-0
Table 9-60. Chip Miscellaneous Control Register (CHIP_MISC_CTL0) Field Descriptions
Bit
31-19
18
17-13
12
11-3
2-0
Field
Reserved
USB_PME_EN
Reserved
MSMC_BLOCK_PARITY_RST
Reserved
QM_PRIORITY
Description
Reserved.
Enables wakeup event generation from USB
• 0 = Disable PME event generation
• 1 = Enable PME event generation
Controls MSMC parity RAM reset. When set to ‘1’ means the MSMC parity RAM will not be reset.
Reserved
Control the priority level for the transactions from QM_Master port, which access the external
linking RAM.
9.2.3.29 Chip Miscellaneous Control (CHIP_MISC_CTL1) Register
Figure 9-46. Chip Miscellaneous Control Register (CHIP_MISC_CTL1)
31
12
Reserved
R- 0
Legend: R = Read only; RW = Read/Write; -n = value after reset
11
DDR3A_PSC_LOCK_n
RW-0
10
0
Reserved
RW-0000000000000
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Device Boot and Configuration 203