TCI6630K2L Datasheet, PDF (70/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
SETTING
Default permission
Number of allowed IDs supported
Number of programmable ranges
supported
Compare width
Table 7-4. MPU12-MPU15 Default Configuration
MPU12
SPI0
Assume allowed
16
2
MPU13
SPI1
Assume allowed
16
2
MPU14
SPI2
Assume allowed
16
2
1KB granularity
1KB granularity
1KB granularity
MPU15
DFE, IQNet, NetCP
Assume allowed
16
16
1KB granularity
MPU0
MPU1
MPU2
MPU3
MPU4
MPU5
MPU6
MPU7
MPU8
MPU9
MPU10
MPU11
MPU12
MPU13
MPU14
MPU15
Table 7-5. MPU Memory Regions
MEMORY PROTECTION
Main CFG SCR
QM_SS DATA PORT
QM_SS CFG1 PORT
Reserved
RAC
QM_SS CFG2 PORT
Reserved
OSR
SPIROM/EMIF16
CIC/AINTC
Semaphore
SCR_6 and CPU/6 CFG SCR
SPI0
SPI1
SPI2
DFE, IQNet, NetCP
START ADDRESS
0x01D0_0000
0x23A0_0000
0x02A0_0000
0x027C_0000
0x0210_0000
0x02A0_4000
0x02C0_0000
0x2101_0000
0x20B0_0000
0x0264_0000
0x0260_0000
0x0220_0000
0x2100_0400
0x2100_0400
0x2100_0800
0x2400_0000
END ADDRESS
0x01e7_FFFF
0x23BF_FFFF
0x02AF_FFFF
0x027C_03FF
0x0215_FFFF
0x02BF_FFFF
0x02CD_FFFF
0xFFFF_FFFF
0x3FFF_FFFF
0x0264_07FF
0x0260_9FFF
0x03FF_FFFF
0x2100_07FF
0x2100_07FF
0x2100_0AFF
0x2508_FFFF
Table 7-6 shows the unique Master ID assigned to each CorePac and peripherals on the device.
MASTER ID
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Table 7-6. Master ID Settings
TCI6630
C66x CorePac0 Data
C66x CorePac1 Data
C66x CorePac2 Data
C66x CorePac3 Data
Reserved
Reserved
Reserved
Reserved
ARM CorePac 0
ARM CorePac 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
C66x CorePac0 CFG
C66x CorePac1 CFG
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Memory, Interrupts, and EDMA for TCI6630K2L
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