TCI6630K2L Datasheet, PDF (2/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
– IQNet Subsystem
• Transporting baseband antenna streams
over two-lane SerDes-based Antenna
Interface Link (AIL)
• Transporting baseband antenna streams to
an integrated Digital Front End (DFE)
• Operating at Up to 9.83 Gbps
• Compliant with OBSAI RP3 and CPRI
Standards for 3G / 4G (WCDMA, LTE TDD,
LTE FDD, TD-SCDMA, and WiMAX)
– Two One-Lane PCIe Gen2 Interfaces
• Supports Up to 5 GBaud
– Three Enhanced Direct Memory Access (EDMA)
Controllers
1.2 Applications
• Small Cell Base Station
• Remote Radio Head
– 72-Bit DDR3 Interface, Speeds Up to 1600 MHz
– EMIF16 Interface
– USB 3.0 Interface
– USIM Interface
– Four UART Interfaces
– Three I²C Interfaces
– 64 GPIO Pins
– Three SPI Interfaces
– Semaphore Module
– Fourteen 64-Bit Timers
• Commercial Case Temperature:
– 0ºC to 100ºC
• Extended Case Temperature:
– -40ºC to 100ºC
• Radio Relay
• Software Defined Radio
1.3 KeyStone Architecture
TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP
cores with application-specific coprocessors and I/O. KeyStone is the first of its kind in that it provides
adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors,
and I/O. This is achieved with four main hardware elements: Multicore Navigator, TeraNet, and Multicore
Shared Memory Controller.
Multicore Navigator is an innovative packet-based manager that controls 8K queues. When tasks are
allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to
the appropriate available hardware. The packet-based system on a chip (SoC) uses the 2-Tbps capacity
of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller
enables processing cores to access shared memory directly without drawing from the TeraNet’s capacity,
so packet movement cannot be blocked by memory access.
1.4 Device Description
The TCI6630K2L Communications Infrastructure KeyStone SoC is a member of the C66x family based on
TI's new KeyStone II Multicore SoC Architecture and is a low-power baseband solution with integrated
digital front end (DFE) that meets the more stringent power, size, and cost requirements of small cell
wireless base stations. In enterprise and pico base stations, the device’s ARM and DSP cores deliver
exceptional processing power on platforms for developing all wireless standards including
WCDMA/HSPA/HSPA+, TD-SCDMA, GSM, TDD-LTE, FDD-LTE, and WiMAX.
TI's KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM
CorePac, C66x CorePacs, IP network, radio layers 1, 2, and 3, and transport processing) and uses a
queue-based communication system that allows the SoC resources to operate efficiently and seamlessly.
This unique SoC architecture also includes a TeraNet switch that enables the wide mix of system
elements, from programmable cores to dedicated coprocessors and high-speed IO, to each operate at
maximum efficiency with no blocking or stalling.
The addition of the ARM CorePac in the TCI6630 enables the ability for layer 2 and layer 3 processing on-
chip. Operations such as Traffic Control, Local O&M, NBAP/FP termination, and SCTP processing can all
be performed with the Cortex-A15 processor.
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TCI6630K2L Features and Description
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