TCI6630K2L Datasheet, PDF (233/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
• Watchdog timer should cause one of the below based on the setting of the CORESEL[2:0] and
RSTCFG registers in the PLL Controller. (See Section 11.5.3.8 and Section 7.3.2.)
– Local reset
– NMI
– NMI followed by a time delay and then a local reset for the C66x CorePac selected
– Hard reset by requesting reset via the PLL Controller
• LPSC MMRs (memory-mapped registers)
For more details see the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide
(SPRUGV2).
11.4.5 ARM CorePac Reset
The ARM CorePac uses a combination of power-on-reset and module-reset to reset its components, such
as the Cortex-A15 processor, memory subsystem, debug logic, etc. The ARM CorePac incorporates the
PSC to generate resets for its internal modules. Details of reset generation and distribution inside the
ARM CorePac can be found in the KeyStone II Architecture ARM CorePac User's Guide (SPRUHJ4).
11.4.6 Reset Priority
If any of the above reset sources occur simultaneously, the PLL Controller processes only the highest
priority reset request. The reset request priorities are as follows (high to low):
• Power-on reset
• Hard/soft reset
11.4.7 Reset Controller Register
The reset controller registers are part of the PLL Controller MMRs. All TCI6630K2L device-specific MMRs
are covered in Section 11.5.3. For more details on these registers and how to program them, see the
KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide (SPRUGV2).
11.4.8 Reset Electrical Data/Timing
Table 11-10. Reset Timing Requirements⁽¹⁾
(see Figure 11-4 and Figure 11-5)
NO.
RESETFULL Pin Reset
1
tw(RESETFULL)
Pulse width - pulse width RESETFULL low
Soft/Hard-Reset
2
tw(RESET)
Pulse width - pulse width RESET low
(1) C = 1/SYSCLK1 clock frequency in ns
Table 11-11. Reset Switching Characteristics⁽¹⁾
(see Figure 11-4 and Figure 11-5)
NO.
PARAMETER
RESETFULL Pin Reset
3
td(RESETFULLH-
RESETSTATH)
Delay time - RESETSTAT high after RESETFULL high
Soft/Hard Reset
4
td(RESETH-RESETSTATH) Delay time - RESETSTAT high after RESET high
(1) C = 1/SYSCLK1 clock frequency in ns
MIN
500C
500C
MAX UNIT
ns
ns
MIN
MAX UNIT
50000C ns
50000C ns
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TCI6630K2L Peripheral Information and Electrical Specifications 233
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