 English |
|
|
|
|
|
|
|
| TCI6630K2L Datasheet, PDF (282/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip | |||
| |||
| ◁ |
TCI6630K2L
SPRS893E â MAY 2013 â REVISED JANUARY 2015
www.ti.com
Table 11-67. EMIF16 Asynchronous Memory Timing Requirements(1) (continued)
(see Figure 11-65 through Figure 11-68)
NO.
21 toh(WEH-BAIV) Output hold time from WE high to BA invalid
22 tosu(AV-WEL) Output setup time from A valid to WE low
23 toh(WEH-AIV) Output hold time from WE high to A invalid
24 tw(WEL)
WE active time low, when ew = 0. Extended wait mode is
disabled.
24 tw(WEL)
WE active time low, when ew = 1. Extended wait mode is
enabled.
26 tosu(DV-WEL) Output setup time from D valid to WE low
27 toh(WEH-DIV) Output hold time from WE high to D invalid
25 td(WAITH-WEH) Delay time from WAIT deasserted to WE# high
MIN
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WST+1) * E - 3
(WST+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
4E + 3 ns
EM_CE[3:0]
EM_R/W
EM_BA[1:0]
EM_A[21:0]
4
6
8
EM_OE
EM_D[15:0]
3
10
12
5
7
9
13
EM_WE
Figure 11-65. EMIF16 Asynchronous Memory Read Timing Diagram
15
EM_CE[3:0]
EM_R/W
EM_BA[1:0]
EM_A[21:0]
16
17
18
19
20
21
22
23
24
EM_WE
26
27
EM_D[15:0]
EM_OE
Figure 11-66. EMIF16 Asynchronous Memory Write Timing Diagram
282 TCI6630K2L Peripheral Information and Electrical Specifications
Copyright © 2013â2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TCI6630K2L
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese