TCI6630K2L Datasheet, PDF (245/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Table 11-25. Reset Isolation Register Field Descriptions
Bit
31-2
1
0
Field
Description
Reserved
Reserved.
SGMIISTISOEN
Isolate SGMII control
• 0 = SGMII SerDes lane reset isolation disabled for all lanes.
• 1 = SGMII SerDes lane reset isolation enabled for all lanes i.e. SerDes lanes will not be reset on Non-POR
chip resets.
AILRSTISOEN
Isolate AIL control
• 0 = AIL SerDes lane reset isolation disabled for all lanes.
• 1 = AIL SerDes lane reset isolation enabled for all lanes i.e. SerDes lanes will not be reset on Non-POR chip
resets.
11.5.4 Main PLL Control Registers
The Main PLL uses two chip-level registers (MAINPLLCTL0 and MAINPLLCTL1) along with the Main PLL
Controller for its configuration. These MMRs (memory-mapped registers) exist inside the Bootcfg space.
To write to these registers, software should go through an unlocking sequence using the KICK0 and
KICK1 registers. These registers reset only on a POR reset.
For valid configurable values of the MAINPLLCTL registers, see Section 9.1.4. See Section 9.2.3.5 for the
address location of the KICK registers and their locking and unlocking sequences.
See Figure 11-19 and Table 11-26 for MAINPLLCTL0 details and Figure 11-20 and Table 11-27 for
MAINPLLCTL1 details.
Figure 11-19. Main PLL Control Register 0 (MAINPLLCTL0)
31
24
23
19
BWADJ[7:0]
Reserved
RW-0000 0101
RW - 0000 0
Legend: RW = Read/Write; -n = value after reset
18
12
PLLM[12:6]
RW-0000000
11
6
Reserved
RW-000000
5
0
PLLD
RW-000000
Table 11-26. Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions
Bit Field
31-24 BWADJ[7:0]
23-19 Reserved
18-12 PLLM[12:6]
Description
BWADJ[11:8] and BWADJ[7:0] are located in MAINPLLCTL0 and MAINPLLCTL1 registers. BWADJ[11:0]
should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
Reserved
7-bits of a 13-bit field PLLM that selects the values for the multiplication factor. PLLM field is loaded with the
multiply factor minus 1.
11-6
5-0
Reserved
PLLD
The PLLM[5:0] bits of the multiplier are controlled by the PLLM register inside the PLL Controller and the
PLLM[12:6] bits are controlled by the above chip-level register. MAINPLLCTL0 register PLLM[12:6] bits should
be written just before writing to PLLM register PLLM[5:0] bits in the controller to have the complete 13 bit value
latched when the GO operation is initiated in the PLL controller. See the KeyStone Architecture Phase Locked
Loop (PLL) Controller User's Guide (SPRUGV2) for the recommended programming sequence. Output Divide
ratio and Bypass enable/disable of the Main PLL is also controlled by the SECCTL register in the PLL
Controller. See Section 11.5.3.1 for more details.
Reserved
A 6-bit field that selects the values for the reference divider. PLLD field is loaded with reference divide value
minus 1.
Figure 11-20. Main PLL Control Register 1 (MAINPLLCTL1)
31
Reserved
RW - 0000000000000000000000000
Legend: RW = Read/Write; -n = value after reset
7
6
5
4
ENSAT
Reserved
RW-0
R-00
3
0
BWADJ[11:8]
RW- 0000
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TCI6630K2L Peripheral Information and Electrical Specifications 245
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