TCI6630K2L Datasheet, PDF (21/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Table 5-1. Cortex-A15 Processor Core Supported Features (continued)
FEATURES
Cortex-A15 processor version
Integer core
NEON core
Architecture Extensions
L1 Lcache and Dcache
L2 cache
Cache Coherency
Branch target address cache
Enhanced memory management
unit
Buses
Non-invasive Debug Support
Misc Debug Support
Voltage
Power
DESCRIPTION
R2P4
Main core for processing integer instructions
Gives greatly enhanced throughput for media workloads and VFP-Lite support
Security, virtualization and LPAE (40-bit physical address) extensions
32KB, 2-way, 16 word line, 128 bit interface
1024KB, 16-way, 16 word line, 128 bit interface to L1, ECC/Parity is supported shared between cores
L2 valid bits cleared by software loop or by hardware
Support for coherent memory accesses between A15 cores and other non-core master peripherals
(Ex: EDMA) in the DDR3A and MSMC SRAM space.
Dynamic branch prediction with Branch Target Buffer (BTB) and Global History Buffer (GHB), a return
stack, and an indirect predictor
Mapping sizes are 4KB, 64KB, 1MB, and 16MB
128b AXI4 internal bus from Cortex-A15 converted to a 256b VBUSM to interface (through the
MSMC) with MSMC SRAM, DDR EMIF, ROM, Interrupt controller and other system peripherals
Processor instruction trace using 4x Program Trace Macrocell (Coresight™ PTM), Data trace (print-f
style debug) using System Trace Macrocell (Coresight™ STM) and Performance Monitoring Units
(PMU)
JTAG based debug and Cross triggering
SmartReflex voltage domain for automatic voltage scaling
Support for standby modes and separate core power domains for additional leakage power reduction
5.3.3 ARM Interrupt Controller
The ARM CorePac interrupt controller (AINTC) is responsible for prioritizing all service requests from the
system peripherals and the secondary interrupt controller CIC2 and then generating either nIRQ or nFIQ
to the Cortex-A15 processor. The type of the interrupt (nIRQ or nFIQ) and the priority of the interrupt
inputs are programmable. The AINTC interfaces to the Cortex-A15 processor via the AXI port through an
VBUS2AXI bridge and runs at half the processor speed. It has the capability to handle up to 480 requests,
which can be steered/prioritized as A15 nFIQ or nIRQ interrupt requests.
The general features of the AINTC are:
• Up to 480 level sensitive shared peripheral interrupts (SPI) inputs
• Individual priority for each interrupt input
• Each interrupt can be steered to nFIQ or nIRQ
• Independent priority sorting for nFIQ and nIRQ
• Secure mask flag
On the chip level, there is a dedicated chip level interrupt controller to serve the ARM interrupt controller.
See Section 7.3 for more details.
The figure below shows an overall view of the ARM CorePac Interrupt Controller.
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