TCI6630K2L Datasheet, PDF (257/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Bit
31-1
0
Field
Reserved
SYNC_EN
Table 11-39. DFE Clock Sync Control Register Field Descriptions
Description
Sync logic enable
• 0 = Sync logic not enabled (default)
• 1 = Sync logic enabled
11.8.4 DFE Electrical Data/Timing
Table 11-40 provides a cross reference between the JESD204B signal names and the TCI6630K2L name.
Table 11-40. TCI6630K2L to JESD204B Signal Name
Cross Reference
TCI6630K2L
DFESYNCIN 0 and 1
DFESYNCOUT 0 and 1
DFESYSREF
SYSCLK
JESD204B
SYNCIN
SYNCOUT
SYSREF
SYSCLK
Table 11-41. DFEIO (0-17) GPIO Input Pulse Timing Requirements
(see Figure 11-40)
NO.
2
tw(DFEGPIL)
PARAMETER
Pulse Duration, DFEGPI Low
MIN
2P ⁽¹⁾
1
tw(DFEGPIH)
Pulse Duration, DFEGPI High
2P
(1) P = 1/SYSCLK clock frequency in ns.
Table 11-42. DFEIO (0-17) GPIO Output Timing Characteristics
(see Figure 11-40)
NO.
4
tw(DFEGPOL)
PARAMETER
Pulse Duration, DFEGPO Low
MIN
2P ⁽¹⁾
3
tw(DFEGPOH)
Pulse Duration, DFEGPO High
2P
(1) P = 1/SYSCLK clock frequency in ns.
1
2
DFEIx
3
4
DFEOx
MAX
UNIT
ns
ns
MAX
UNIT
ns
ns
Figure 11-40. DFEIO (0-17) GPIO Input/Output
Table 11-43. DFESYNCIN Sync Input Pulse Timing Requirements
(see Figure 11-41)
NO.
2
tw(DFESYNCINN0L)
PARAMETER
Pulse Duration, DFESYNCIN(N)0 Low
MIN
2P ⁽¹⁾
1
tw(DFESYNCINN0H)
Pulse Duration, DFESYNCIN(N)0 High
2P
2
tw(DFESYNCINP0L)
Pulse Duration, DFESYNCIN(P)0 Low
2P
1
tw(DFESYNCINP0H)
Pulse Duration, DFESYNCIN(P)0 High
2P
MAX
UNIT
ns
ns
ns
ns
(1) P = 1/SYSCLK clock frequency in ns.
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TCI6630K2L Peripheral Information and Electrical Specifications 257
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