TCI6630K2L Datasheet, PDF (15/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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L2 Mode Bits
000
001
010
011
100
101
110
TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
L2 Memory
Block Base
Address
0080 0000h
1/2
SRAM
ALL
SRAM
31/32
SRAM
15/16
SRAM
7/8
SRAM
3/4
SRAM
4-Way
Cache
512K bytes
0088 0000h
256K bytes
4-Way
Cache
008C 0000h
128K bytes
4-Way
Cache
4-Way
Cache
4-Way
Cache
4-Way
Cache
64K bytes
32K bytes
32K bytes
008E 0000h
008F 0000h
008F 8000h
008F FFFFh
Figure 4-4. L2 Memory Configurations
Global addresses that are accessible to all masters in the system are in all memory local to the
processors. In addition, local memory can be accessed directly by the associated processor through
aliased addresses, where the eight MSBs are masked to 0. The aliasing is handled within the CorePac
and allows for common code to be run unmodified on multiple cores. For example, address location
0x10800000 is the global base address for CorePac0's L2 memory. CorePac0 can access this location by
either using 0x10800000 or 0x00800000. Any other master on the device must use 0x10800000 only.
Conversely, 0x00800000 can by used by any of the C66x CorePacs as their own L2 base addresses. For
CorePac0, as mentioned, this is equivalent to 0x10800000, for CorePac1 this is equivalent to
0x11800000, and for CorePac2 this is equivalent to 0x12800000. Local addresses should be used only for
shared code or data, allowing a single image to be included in memory. Any code/data targeted to a
specific core, or a memory region allocated during run-time by a particular CorePac should always use the
global address only.
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