TCI6630K2L Datasheet, PDF (66/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
Table 7-1. Device Memory Map Summary for TCI6630K2L (continued)
PHYSICAL 40 BIT ADDRESS
START
END
00 0285 8000 00 0285 FFFF
00 0286 0000 00 028F FFFF
00 0290 0000 00 0293 FFFF
00 0294 0000 00 029F FFFF
00 02A0 0000 00 02AF FFFF
00 02B0 0000 00 02BF FFFF
00 02C0 0000 00 02C0 FFFF
00 02C1 0000 00 02C1 FFFF
00 02C2 0000 00 02C3 FFFF
00 02C4 0000 00 02C5 FFFF
00 02C6 0000 00 02C7 FFFF
00 02C8 0000 00 02C8 FFFF
00 02C9 0000 00 02C9 FFFF
00 02CA 0000 00 02CB FFFF
00 02CC 0000 00 02CD FFFF
00 02CE 0000 00 02EF FFFF
00 02F0 0000 00 02FF FFFF
00 0300 0000 00 030F FFFF
00 0310 0000 00 07FF FFFF
00 0800 0000 00 0801 FFFF
BYTES
32K
640K
256K
768K
1M
1M
64K
64K
128K
128K
128K
64K
64K
128K
128K
15M-896K
1M
1M
79M
128K
00 0802 0000 00 0BBF FFFF 60M-128K
00 0BC0 0000 00 0BCF FFFF 1M
00 0BD0 0000
00 0C00 0000
00 0C20 0000
00 1000 0000
00 1080 0000
00 1090 0000
00 10E0 0000
00 10E0 8000
00 10F0 0000
00 10F0 8000
00 1180 0000
00 1190 0000
00 11E0 0000
00 11E0 8000
00 11F0 0000
00 11F0 8000
00 1280 0000
00 1290 0000
00 12E0 0000
00 12E0 8000
00 12F0 0000
00 12F0 8000
00 1380 0000
00 1390 0000
00 13E0 0000
00 13E0 8000
00 13F0 0000
00 0BFF FFFF
00 0C1F FFFF
00 0FFF FFFF
00 107F FFFF
00 108F FFFF
00 10DF FFFF
00 10E0 7FFF
00 10EF FFFF
00 10F0 7FFF
00 117F FFFF
00 118F FFFF
00 11DF FFFF
00 11E0 7FFF
00 11EF FFFF
00 11F0 7FFF
00 127F FFFF
00 128F FFFF
00 12DF FFFF
00 12E0 7FFF
00 12EF FFFF
00 12F0 7FFF
00 137F FFFF
00 1388 FFFF
00 13DF FFFF
00 13E0 7FFF
00 13EF FFFF
00 13F0 7FFF
3M
2M
62M
8M
1M
5M
32K
1M-32K
32K
9M-32K
1M
5M
32K
1M-32K
32K
9M-32K
1M
5M
32K
1M-32K
32K
9M-32K
1M
5M
32K
1M-32K
32K
ARM VIEW
Reserved
Reserved
Reserved
Reserved
Navigator configuration
Navigator linking RAM
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Debug_SS Configuration
Reserved
Extended memory controller
(XMC) configuration
Reserved
Multicore shared memory
controller (MSMC) config
Reserved
Multicore shared memory (MSM)
Reserved
Reserved
CorePac0 L2 SRAM
Reserved
CorePac0 L1P SRAM
Reserved
CorePac0 L1D SRAM
Reserved
CorePac1 L2 SRAM
Reserved
CorePac1 L1P SRAM
Reserved
CorePac1 L1D SRAM
Reserved
CorePac2 L2 SRAM
Reserved
CorePac2 L1P SRAM
Reserved
CorePac2 L1D SRAM
Reserved
CorePac3 L2 SRAM
Reserved
CorePac3 L1P SRAM
Reserved
CorePac3 L1D SRAM
DSP VIEW
Reserved
Reserved
Reserved
Reserved
Navigator configuration
Navigator linking RAM
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Debug_SS Configuration
Reserved
Extended memory controller
(XMC) configuration
Reserved
Multicore shared memory
controller (MSMC) config
Reserved
Multicore shared memory (MSM)
Reserved
Reserved
CorePac0 L2 SRAM
Reserved
CorePac0 L1P SRAM
Reserved
CorePac0 L1D SRAM
Reserved
CorePac1 L2 SRAM
Reserved
CorePac1 L1P SRAM
Reserved
CorePac1 L1D SRAM
Reserved
CorePac2 L2 SRAM
Reserved
CorePac2 L1P SRAM
Reserved
CorePac2 L1D SRAM
Reserved
CorePac3 L2 SRAM
Reserved
CorePac3 L1P SRAM
Reserved
CorePac3 L1D SRAM
SOC VIEW
Reserved
Reserved
Reserved
Reserved
Navigator configuration
Navigator linking RAM
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Debug_SS Configuration
Reserved
Extended memory controller
(XMC) configuration
Reserved
Multicore shared memory
controller (MSMC) config
Reserved
Multicore shared memory (MSM)
Reserved
Reserved
CorePac0 L2 SRAM
Reserved
CorePac0 L1P SRAM
Reserved
CorePac0 L1D SRAM
Reserved
CorePac1 L2 SRAM
Reserved
CorePac1 L1P SRAM
Reserved
CorePac1 L1D SRAM
Reserved
CorePac2 L2 SRAM
Reserved
CorePac2 L1P SRAM
Reserved
CorePac2 L1D SRAM
Reserved
CorePac3 L2 SRAM
Reserved
CorePac3 L1P SRAM
Reserved
CorePac3 L1D SRAM
66
Memory, Interrupts, and EDMA for TCI6630K2L
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