TCI6630K2L Datasheet, PDF (250/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
<CLK_NAME>CLKN
<CLK_NAME>CLKP
1
2
3
4
5
Figure 11-24. Clock Input Timing
www.ti.com
peak-to-peak Differential Input
Voltage (250 mV to 2 V)
0
200 mV Transition Voltage Range
T_R = 50 ps Min to 350 ps Max
for the 200-mV Transition Voltage Range
Figure 11-25. Main PLL Transition Time
T_C Reference Clock Period
peak-to-peak
Differential
Input Voltage
0
(400 mV to 1100 mV)
10% to 90%
of peak-to-peak
Voltage
Max T_R = 0.2 _× T_C from
10% to 90% of the
peak-to-peak
Differential Voltage
Max T_F = 0.2 _× T_C from
90% to 10% of the
peak-to-peak
Differential Voltage
Figure 11-26. Rise and Fall Times (except for USB clock)
T_C Reference Clock Period
peak-to-peak
Differential
Input Voltage
0
(300 mV to 850 mV)
10% to 90%
of peak-to-peak
Voltage
T_R = 75 ps Min to 500 ps Max
for 300 mv Transition
Voltage Range
T_F = 75 ps Min to 500 ps Max
for 300 mv Transition
Voltage Range
Figure 11-27. USBCLK Rise and Fall Times
250 TCI6630K2L Peripheral Information and Electrical Specifications
Copyright © 2013–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TCI6630K2L