TCI6630K2L Datasheet, PDF (252/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
Figure 11-30. DDR3A PLL Control Register 1 (DDR3APLLCTL1)
31
15
14
Reserved
PLLRST
RW - 00000000000000000
RW-0
Legend: RW = Read/Write; -n = value after reset
13
7
Reserved
RW-0000000
6
ENSAT
RW-0
5
4
Reserved
R-00
3
0
BWADJ[11:8]
RW- 0000
Bit
31-15
14
Field
Reserved
PLLRST
13-7
6
5-4
3-0
Reserved
ENSAT
Reserved
BWADJ[11:8]
Table 11-32. DDR3A PLL Control Register 1 Field Descriptions
Description
Reserved
PLL Reset bit
• 0 = PLL Reset is released
• 1 = PLL Reset is asserted
Reserved
Needs to be set to 1 for proper PLL operation
Reserved
BWADJ[11:8] and BWADJ[7:0] are located inDDR3APLLCTL0 and DDR3APLLCTL1 registers. BWADJ[11:0]
should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
11.6.2 DDR3A PLL Device-Specific Information
As shown in Figure 11-28, the output of DDR3A PLL (PLLOUT) is divided by 2 and directly fed to the
DDR3A memory controller. During power-on resets, the internal clocks of the DDR3 PLL are affected as
described in Section Section 11.4. The DDR3 PLL is unlocked only during the power-up sequence and is
locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.
11.6.3 DDR3 PLL Input Clock Electrical Data/Timing
Table 11-33 applies to DDR3A memory interface.
Table 11-33. DDR3 PLL DDRCLK(N|P) Timing Requirements
(see Figure 11-31 and Figure 11-25)
No.
Min
DDRCLK[P:N]
1 tc(DDRCLKN)
Cycle time _ DDRCLKN cycle time
3.2
1 tc(DDRCLKP)
Cycle time _ DDRCLKP cycle time
3.2
3 tw(DDRCLKN)
Pulse width _ DDRCLKN high
0.45*tc(DDRCLKN)
2 tw(DDRCLKN)
Pulse width _ DDRCLKN low
0.45*tc(DDRCLKN)
2 tw(DDRCLKP)
Pulse width _ DDRCLKP high
0.45*tc(DDRCLKP)
3 tw(DDRCLKP)
Pulse width _ DDRCLKP low
0.45*tc(DDRCLKP)
4 tr(DDRCLK_200
mV)
Transition time _ DDRCLK differential rise time (200 mV)
50
4 tf(DDRCLK_200
mV)
Transition time _ DDRCLK differential fall time (200 mV)
50
5 tj(DDRCLKN)
Jitter, peak_to_peak _ periodic DDRCLKN
5 tj(DDRCLKP)
Jitter, peak_to_peak _ periodic DDRCLKP
Max Unit
25 ns
25 ns
0.55*tc(DDRCLKN) ns
0.55*tc(DDRCLKN) ns
0.55*tc(DDRCLKP) ns
0.55*tc(DDRCLKP) ns
350 ps
350 ps
0.02*tc(DDRCLKN) ps
0.02*tc(DDRCLKP) ps
DDRCLKN
1
2
3
DDRCLKP
4
5
Figure 11-31. DDR3 PLL DDRCLK Timing
252 TCI6630K2L Peripheral Information and Electrical Specifications
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