TCI6630K2L Datasheet, PDF (10/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
( _ ) TCI 66 30 K2 L ( _ ) ( _ ) CMS ( _ ) ( _ )
PREFIX
X = Experimental device
Blank = Qualified device
DEVICE SPEED RANGE
Blank = 1 GHz
2 = 1.2 GHz
DEVICE FAMILY
TCI = System on Chip
DEVICE CORE
66 = C66 DSP Family
DEVICE NUMBER
30
TEMPERATURE RANGE
Blank = 0°C to +100°C (default case temperature)
A = Extended temperature range (-40°C to +100°C)
PACKAGE TYPE
CMS = 900-pin plastic ball grid array,
with Pb-free solder balls and die bumps
ARCHITECTURE
K2 = KeyStone II
PLATFORM
L
SILICON REVISION
Blank = Initial 1.0 silicon
SECURITY
Blank = Security Accelerator disabled / General Purpose device
X = Security Accelerator enabled / General Purpose device
D = Security Accelerator enabled / High Security device
with TI developmental keys
S = Security Accelerator enabled / High Security device
with production keys
Figure 3-1. C66x DSP Device Nomenclature (including the TCI6630K2L)
3.5 Related Documentation from Texas Instruments
These documents describe the TCI6630K2L Multicore ARM+DSP KeyStone II System-on-Chip (SoC).
Copies of these documents are available on the Internet at www.ti.com.
KeyStone Architecture Timer 64P User's Guide
KeyStone II Architecture ARM Bootloader User's Guide
KeyStone Architecture Chip Interrupt Controller (CIC) User's Guide
KeyStone I Architecture Debug and Trace User's Guide
DDR3 Design Requirements for KeyStone Devices application report
KeyStone Architecture DDR3 Memory Controller User's Guide
KeyStone Architecture External Memory Interface (EMIF16) User's Guide
Emulation and Trace Headers Technical Reference Manual
KeyStone Architecture Enhanced Direct Memory Access 3 (EDMA3) User's Guide
KeyStone Architecture General Purpose Input/Output (GPIO) User's Guide
Gigabit Ethernet (GbE) Switch Subsystem (1 GB) User's Guide
Hardware Design Guide for KeyStone II Devices application report
KeyStone Architecture Inter-IC control Bus (I²C) User's Guide
KeyStone Architecture Memory Protection Unit (MPU) User's Guide
KeyStone Architecture Multicore Navigator User's Guide
KeyStone II Architecture Multicore Shared Memory Controller (MSMC) User's Guide
KeyStone II Architecture Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide
Optimizing Application Software on KeyStone Devices application report
KeyStone II Architecture Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide
KeyStone Architecture Peripheral Component Interconnect Express (PCIe) User's Guide
KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide
KeyStone Architecture Power Sleep Controller (PSC) User's Guide
KeyStone II Architecture Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide
Security Addendum for KeyStone II Devices application report⁽¹⁾
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(1) Contact a TI sales office to obtain this document.
10
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