TCI6630K2L Datasheet, PDF (249/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Table 11-30. Main PLL Controller/ARM/DFE/PCIe/Shared SerDes/USB/TSREF Clock Input Timing
Requirements⁽¹⁾ (continued)
(see Figure 11-24 through Figure 11-27)
NO.
MIN
MAX
5
tj(SHARED_SERDES_0_ Jitter, RMS SHARED_SERDES_0_REFCLKP
REFCLKP)
4
SHARED_SERDES_1_REFCLK[P:N]
1
tc(SHARED_SERDES_1_ Cycle time SHARED_SERDES_1_REFCLKN
REFCLKN)
cycle time
8.138
1
tc(SHARED_SERDES_1_ Cycle time SHARED_SERDES_1_REFCLKP
REFCLKP)
cycle time
8.138
3
tw(SHARED_SERDES_1_ Pulse width SHARED_SERDES_1_REFCLKN
0.45*tc(SHARED_
0.55*tc(SHARED_
REFCLKN)
high
SERDES_1_REFCLKN) SERDES_1_REFCLKN)
2
tw(SHARED_SERDES_1_ Pulse width SHARED_SERDES_1_REFCLKN
0.45*tc(SHARED_
0.55*tc(SHARED_
REFCLKN)
low
SERDES_1_REFCLKN) SERDES_1_REFCLKN)
2
tw(SHARED_SERDES_1_ Pulse width SHARED_SERDES_1_REFCLKP
0.45*tc(SHARED_
0.55*tc(SHARED_
REFCLKP)
high
SERDES_1_REFCLKP) SERDES_1_REFCLKP)
3
tw(SHARED_SERDES_1_ Pulse width SHARED_SERDES_1_REFCLKP
0.45*tc(SHARED_
0.55*tc(SHARED_
REFCLKP)
low
SERDES_1_REFCLKP) SERDES_1_REFCLKP)
4
tr(SHARED_SERDES_1_ Rise time SHARED_SERDES_1_REFCLK
REFCLK[P:N])
differential rise time (10% to 90%)
0.2*tc(SHARED_SERDES
_1_REFCLK[P:N])
4
tf(SHARED_SERDES_1_ Fall time CSISC2_0REFCLK differential fall time
REFCLK[P:N])
(10% to 90%)
0.2*tc(SHARED_SERDES
_1_REFCLK[P:N])
5
tj(CSISC2_0REFCLKN) Jitter, RMS CSISC2_0REFCLKN
4
5
tj(CSISC2_0REFCLKP) Jitter, RMS CSISC2_0REFCLKP
4
USBCLK[P:M]
1
tc(USBCLKN)
Cycle time USBCLKN cycle time
10
10
1
tc(USBCLKP)
Cycle time USBCLKP cycle time
10
10
3
tw(USBCLKN)
Pulse width USBCLKN high
0.45*tc(USBCLKN)
0.55*tc(USBCLKN)
2
tw(USBCLKN)
Pulse width USBCLKN low
0.45*tc(USBCLKN)
0.55*tc(USBCLKN)
2
tw(USBCLKP)
Pulse width USBCLKP high
0.45*tc(USBCLKP)
0.55*tc(USBCLKP)
3
tw(USBCLKP)
Pulse width USBCLKP low
0.45*tc(USBCLKP)
0.55*tc(USBCLKP)
4
tr(USBCLK[P:M])
Rise time USBCLK[P:M] differential rise time
(10% to 90%)
75
500
4
tf(USBCLK[P:M])
Fall time USBCLK[P:M] differential fall time (10%
to 90%)
75
500
5
tj(USBCLKN)
Jitter, RMS USBCLKN
3
5
tj(USBCLKP)
Jitter, RMS USBCLKP
3
TSREFCLK[P:N] ⁽³⁾
1
tc(TSREFCLKN)
Cycle time TSREFCLKN cycle time
3.25
32.55
1
tc(TSREFCLKP)
Cycle time TSREFCLKP cycle time
3.25
32.55
3
tw(TSREFCLKN)
Pulse width TSREFCLKN high
0.45*tc(TSREFCLKN)
0.55*tc(TSREFCLKN)
2
tw(TSREFCLKN)
Pulse width TSREFCLKN low
0.45*tc(TSREFCLKN)
0.55*tc(TSREFCLKN)
2
tw(TSREFCLKP)
Pulse width TSREFCLKP high
0.45*tc(TSREFCLKP)
0.55*tc(TSREFCLKP)
3
tw(TSREFCLKP)
Pulse width TSREFCLKP low
0.45*tc(TSREFCLKP)
0.55*tc(TSREFCLKP)
4
tr(TSREFCLK[P:N])
Rise time TSREFCLK differential rise time (10%
to 90%)
50
350
4
tf(TSREFCLK[P:N])
Fall time TSREFCLK differential fall time (10% to
90%)
50
350
5
tj(TSREFCLKN)
Jitter, RMS TSREFCLKN
5.8
5
tj(TSREFCLKP)
Jitter, RMS TSREFCLKP
5.8
(3) TSREFCLK clock input is LVDS compliant
UNIT
ps, RMS
ns
ns
ns
ns
ns
ns
ps
ps
ps, RMS
ps, RMS
ns
ns
ns
ns
ns
ns
ps
ps
ps, RMS
ps, RMS
ns
ns
ns
ns
ns
ns
ps
ps
ps, RMS
ps, RMS
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TCI6630K2L Peripheral Information and Electrical Specifications 249
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