TCI6630K2L Datasheet, PDF (193/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
These registers also provide a Source ID facility identifying up to 28 different sources of interrupts.
Allocation of source bits to source processor and meaning is entirely based on software convention. The
register field descriptions are given in the following tables. There can be numerous sources for these
registers as this is completely controlled by software. Any master that has access to BOOTCFG module
space can write to these registers. The IPC Generation Register is shown in Figure 9-27 and described in
Table 9-43.
Figure 9-27. IPC Generation Registers (IPCGRx)
31
SRCS27 - SRCS0
RW +0 (per bit field)
Legend: R = Read only; RW = Read/Write; -n = value after reset
4
3
0
Reserved
R-0000
Bit
31-4
Field
SRCSx
3-1 Reserved
0
IPCG
Table 9-43. IPC Generation Registers Field Descriptions
Description
Reads return current value of internal register bit.
Writes:
• 0 = No effect
• 1 = Sets both SRCSx and the corresponding SRCCx.
Reserved
Reads return 0.
Writes:
• 0 = No effect
• 1 = Creates an inter-DSP interrupt.
9.2.3.16 IPC Acknowledgment (IPCARx) Registers
The IPCARx registers facilitate inter-CorePac interrupt acknowledgment.
The TCI6630K2L device has six IPCARx registers.These registers also provide a Source ID facility by
which up to 28 different sources of interrupts can be identified. Allocation of source bits to source
processor and meaning is entirely based on software convention. The register field descriptions are given
in the following tables. Virtually anything can be a source for these registers as this is completely
controlled by software. Any master that has access to BOOTCFG module space can write to these
registers. The IPC Acknowledgment Register is shown in the following figure and table.
Figure 9-28. IPC Acknowledgment Registers (IPCARx)
31
SRCC27 - SRCC0
RW +0 (per bit field)
Legend: R = Read only; RW = Read/Write; -n = value after reset
4
3
0
Reserved
R-0000
Bit
31-4
Field
SRCCx
3-0 Reserved
Table 9-44. IPC Acknowledgment Registers Field Descriptions
Description
Reads return current value of internal register bit.
Writes:
• 0 = No effect
• 1 = Clears both SRCCx and the corresponding SRCSx
Reserved
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Device Boot and Configuration 193