TCI6630K2L Datasheet, PDF (266/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
Table 11-51. SPI Switching Characteristics (continued)
(see Figure 11-47 and Figure 11-48)
NO.
PARAMETER
MIN
4
td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge
on SPICLK Polarity = 1, Phase = 1
5
td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to
initial edge on SPICLK. Polarity = 0 Phase = 0
5
td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to
initial edge on SPICLK Polarity = 0 Phase = 1
5
td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to
initial edge on SPICLK Polarity = 1 Phase = 0
5
td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to
initial edge on SPICLK Polarity = 1 Phase = 1
6
toh(SPC-
SPIDOUT)
Output hold time, SPIDOUT valid after receive edge of
SPICLK except for final bit. Polarity = 0 Phase = 0
0.5*tc - 2
6
toh(SPC-
SPIDOUT)
Output hold time, SPIDOUT valid after receive edge of
SPICLK except for final bit. Polarity = 0 Phase = 1
0.5*tc - 2
6
toh(SPC-
SPIDOUT)
Output hold time, SPIDOUT valid after receive edge of
SPICLK except for final bit. Polarity = 1 Phase = 0
0.5*tc - 2
6
toh(SPC-
SPIDOUT)
Output hold time, SPIDOUT valid after receive edge of
SPICLK except for final bit. Polarity = 1 Phase = 1
0.5*tc - 2
Additional SPI Master Timings — 4 Pin Mode with Chip Select Option
19 td(SCS-SPC)
Delay from SPISCSx\ active to first SPICLK. Polarity = 0
Phase = 0
2*P2 - 5
19 td(SCS-SPC)
Delay from SPISCSx\ active to first SPICLK. Polarity = 0
Phase = 1
0.5*tc + (2*P2) - 5
19 td(SCS-SPC)
Delay from SPISCSx\ active to first SPICLK. Polarity = 1
Phase = 0
2*P2 - 5
19 td(SCS-SPC)
Delay from SPISCSx\ active to first SPICLK. Polarity = 1
Phase = 1
0.5*tc + (2*P2) - 5
20 td(SPC-SCS)
Delay from final SPICLK edge to master deasserting
SPISCSx\. Polarity = 0 Phase = 0
1*P2 - 5
20 td(SPC-SCS)
Delay from final SPICLK edge to master deasserting
SPISCSx\. Polarity = 0 Phase = 1
0.5*tc + (1*P2) - 5
20 td(SPC-SCS)
Delay from final SPICLK edge to master deasserting
SPISCSx\. Polarity = 1 Phase = 0
1*P2 - 5
20 td(SPC-SCS)
Delay from final SPICLK edge to master deasserting
SPISCSx\. Polarity = 1 Phase = 1
0.5*tc + (1*P2) - 5
tw(SCSH)
Minimum inactive time on SPISCSx\ pin between two transfers
when SPISCSx\ is not held using the CSHOLD feature.
2*P2 - 5
MAX UNIT
5 ^ns
2 ^ns
2 ^ns
2 ^ns
2 ^ns
ns
ns
ns
ns
2*P2 + 5 ^ns
0.5*tc + (2*P2) + 5 ^ns
2*P2 + 5 ^ns
0.5*tc + (2*P2) + 5 ^ns
1*P2 + 5 ^ns
0.5*tc + (1*P2) + 5 ^ns
1*P2 + 5 ^ns
0.5*tc + (1*P2) + 5 ^ns
ns
266 TCI6630K2L Peripheral Information and Electrical Specifications
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