TCI6630K2L Datasheet, PDF(29/298 Page) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L Datasheet, PDF (29/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L

SPRS893E â MAY 2013 â REVISED JANUARY 2015

Table 6-2. Terminal Functions â Signals and Control by Function (continued)

SIGNAL NAME

BOOTMODE08B

BOOTMODE09B

BOOTMODE10B

BOOTMODE11B

BOOTMODE12B

BOOTMODE13B

BALL

NO.

H29

J27

H28

G28

H27

AE5

BOOTMODE14B

BOOTMODE15B

LENDIANB

MAINPLL_OD_SELB

AG6

AH6

G26

J30

ALTCORECLKN

ALTCORECLKP

BOOTCOMPLETE

CORECLKSEL0

CORECLKSEL1

CORESEL0

CORESEL1

CORESEL2

DDR3ACLKN

DDR3ACLKP

HOUT

LRESET

LRESETNMIEN

NMI

PCIECLKN

PCIECLKP

POR

RESET

RESETFULL

RESETSTAT

SGMIICLKN

SGMIICLKP

SYSCLKN

SYSCLKP

SYSCLKOUT

TSREFCLKN

TSREFCLKP

TSRXCLKOUT0N

TSRXCLKOUT0P

AH30

AG30

AG3

AE27

AF27

AE5

AG6

AH6

G30

F30

AH2

AK3

AF2

AJ2

AE19

AE20

G4

AF3

AE2

AE4

AF24

AF23

AG29

AF29

AF28

AK14

AK13

AJ13

AJ12

TYPE IPD/IPU

IOZ Down

IOZ Down

IOZ Down

IOZ Down

IOZ Down

I

Down

I

Down

I

Down

IOZ Up

IOZ Down

I

I

O

Down

I

Down

I

Down

I

Down

I

Down

I

Down

I

I

O

Up

I

Up

I

Up

I

Up

I

I

I

I

Up

I

Up

O

Up

I

I

I

I

O

Down

I

I

O

O

DESCRIPTION

User-defined boot mode pins. (B pins are secondary functions and are shared with GPIO[09:13])

Select for the target core for LRESET and NMI. (B pin is a secondary function and is shared with

CORESEL0)

User-defined boot mode pin. (B pin is a secondary function and is shared with CORESEL1)

User-defined boot mode pin. (B pin is a secondary function and is shared with CORESEL2)

Little endian configuration pin. (B pin is a secondary function and is shared with GPIO00)

Main PLL output divider select. (B pin is a secondary function and is shared with GPIO14)

Clock / Reset

System clock input to antenna interface and main PLL (Main PLL optional vs. ALTCORECLK)

Boot progress indication output

Ref clock select for core/ARM/PA PLL

Select for the target core for LRESET and NMI

DDR3A reference clock input to DDR PLL

Interrupt output pulse created by IPCGRH

Warm reset

Enable for core selects

Non-maskable interrupt

PCIe reference clock to drive the PCIe SerDes. Not used when PCIe is not selected

Power-on reset

Warm reset of non isolated portion on the IC

Full reset

Reset status output. Drives low during power-on reset (no HHV override). Available after core and IOs

are are completely powered-up.

SGMII reference clock to drive the SGMII SerDes

System clock input to antenna interface and main PLL (Main PLL optional vs. ALTCORECLK)

System clock output to be used as a general purpose output clock for debug purposes

Clock from external OCXO/VCXO for SyncE

SerDes recovered clock output for SyncE.

Copyright Â© 2013â2015, Texas Instruments Incorporated

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