TCI6630K2L Datasheet, PDF (37/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Table 6-2. Terminal Functions — Signals and Control by Function (continued)
SIGNAL NAME
BALL
NO.
EXTFRAMEEVENT
PHYSYNC
RADSYNC
RP1CLKN²
RP1CLKP²
RP1FBN²
RP1FBP²
AE3
AJ29
AH28
AG13
AG12
AF11
AF10
TCK
AJ3
TDI
AJ4
TDO
AH4
TMS
AH3
TRST
AK4
MDCLK
G2
MDIO
H1
SHARED_SERDES_
0_REFCLKN
SHARED_SERDES_
0_REFCLKP
SHARED_SERDES_
0_REFRES
SHARED_SERDES_
1_REFCLKN
SHARED_SERDES_
1_REFCLKP
SHARED_SERDES_
1_REFRES
SHARED_SERDES_
1_RXN0
SHARED_SERDES_
1_RXN1
SHARED_SERDES_
1_RXP0
SHARED_SERDES_
1_RXP1
SHARED_SERDES_
1_TXN0
SHARED_SERDES_
1_TXN1
SHARED_SERDES_
1_TXP0
SHARED_SERDES_
1_TXP1
SHARED_SERDES_
2_RXN0
SHARED_SERDES_
2_RXP0
SHARED_SERDES_
2_TXN0
SHARED_SERDES_
2_TXP0
AF18
AF17
AE17
AF15
AF14
AE13
AJ16
AK17
AJ15
AK16
AH14
AG15
AH15
AG16
AJ25
AJ24
AH23
AH24
TYPE IPD/IPU
O
Down
I
Down
I
Down
I
I
I
I
I
Up
I
Up
OZ Up
I
Up
I
Down
O
Down
IOZ Up
I
I
DESCRIPTION
IQN
CPRI, OBSAI or radio external frame reference
Non-OBSAI CPRI input sync
Non-OBSAI radio sync
OBSAI RP1 sync clock (² pin is a secondary function and is shared with DFESYNCINN0)
OBSAI RP1 sync clock (² pin is a secondary function and is shared with DFESYNCINP0)
OBSAI RP1 sync (² pin is a secondary function and is shared with DFESYNCINN1)
OBSAI RP1 sync (² pin is a secondary function and is shared with DFESYNCINP1)
JTAG
JTAG clock input
JTAG data input
JTAG data output
JTAG test mode input
JTAG reset
MDIO
MDIO Clock
MDIO Data
JESD
Clock for CSISC2_0 B4 SerDes Marco
A
CSISC2_0 SerDes reference resistor input (3 kΩ ±1%)
I
Clock for CSISC2_1
I
A
CSISC2_1 macro reference resistor input (3 kΩ ±1%)
I
I
CSISC2_1 RX
I
I
O
O
CSISC2_1 TX
O
O
I
Ethernet MAC SGMII receive data
I
O
Ethernet MAC SGMII transmit data
O
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