TCI6630K2L Datasheet, PDF (74/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
Table 7-7. Privilege ID Settings (continued)
PRIVILEGE
ID
MASTER
9
All Packet DMA masters (NetCP,
QM_CDMA, FFTC, BCP_CDMA,
IQNet_CDMA, and USB
10
QM_Second ⁽¹⁾
11
PCIe 0
12
DAP
13
RAC_TAC/BCP_DIO
14
PCIe 1
15
Reserved
PRIVILEGE LEVEL
User mode and supervisor mode is determined
by per transaction basis. Only the transaction
with source ID matching the value in
SupervisorID register is granted supervisor
mode.
User
Supervisor
Driven by Emulation SW
Supervisor
Supervisor
SECURITY
LEVEL
Non-secure
Non-secure
Non-secure
Driven by
Emulation SW
Non-secure
Non-secure
ACCESS
TYPE
DMA
DMA
DMA
DMA
DMA
DMA
(1) QM_Second provides a path that PDSP uses to access the system memory.
7.2.1 MPU Registers
This section includes the offsets for MPU registers and definitions for device-specific MPU registers. For
Number of Programmable Ranges supported (PROGx_MPSA, PROGxMPEA) refer to the following tables.
7.2.1.1 MPU Register Map
OFFSET
0h
4h
10h
14h
18h
1Ch
20h
200h
204h
208h
210h
214h
218h
220h
224h
228h
230h
234h
238h
240h
244h
248h
250h
254h
258h
260h
NAME
REVID
CONFIG
IRAWSTAT
IENSTAT
IENSET
IENCLR
EOI
PROG0_MPSAR
PROG0_MPEAR
PROG0_MPPAR
PROG1_MPSAR
PROG1_MPEAR
PROG1_MPPAR
PROG2_MPSAR
PROG2_MPEAR
PROG2_MPPAR
PROG3_MPSAR
PROG3_MPEAR
PROG3_MPPAR
PROG4_MPSAR
PROG4_MPEAR
PROG4_MPPAR
PROG5_MPSAR
PROG5_MPEAR
PROG5_MPPAR
PROG6_MPSAR
Table 7-8. MPU Registers
DESCRIPTION
Revision ID
Configuration
Interrupt raw status/set
Interrupt enable status/clear
Interrupt enable
Interrupt enable clear
End of interrupt
Programmable range 0, start address
Programmable range 0, end address
Programmable range 0, memory page protection attributes
Programmable range 1, start address
Programmable range 1, end address
Programmable range 1, memory page protection attributes
Programmable range 2, start address
Programmable range 2, end address
Programmable range 2, memory page protection attributes
Programmable range 3, start address
Programmable range 3, end address
Programmable range 3, memory page protection attributes
Programmable range 4, start address
Programmable range 4, end address
Programmable range 4, memory page protection attributes
Programmable range 5, start address
Programmable range 5, end address
Programmable range 5, memory page protection attributes
Programmable range 6, start address
74
Memory, Interrupts, and EDMA for TCI6630K2L
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