TCI6630K2L Datasheet, PDF (230/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
OFFSET
0xAB8
0xABC
0xAC0
0xAC4
0xAC8
0xACC
0xAD0
0xAD4 - 0xFFC
REGISTER
MDCTL46
MDCTL47
MDCTL48
MDCTL49
MDCTL50
MDCTL51
MDCTL52
Reserved
Table 11-8. PSC Register Memory Map (continued)
DESCRIPTION
Module Control Register 46
Module Control Register 47
Module Control Register 48
Module Control Register 49
Module Control Register 50
Module Control Register 51
Module Control Register 52
Reserved
11.4 Reset Controller
The reset controller detects the different type of resets supported on the TCI6630K2L device and
manages the distribution of those resets throughout the device. The device has the following types of
resets:
• Power-on reset
• Hard reset
• Soft reset
• Local reset
Table 11-9 explains further the types of reset, the reset initiator, and the effects of each reset on the
device. For more information on the effects of each reset on the PLL controllers and their clocks, see
Section Section 11.4.8.
Table 11-9. Reset Types
TYPE
INITIATOR
EFFECT(S)
Power-on reset
POR pin
RESETFULL pin
Resets the entire chip including the test and emulation logic. The device configuration pins
are latched only during power-on reset.
Hard reset
RESET pin
PLLCTL Register
(RSCTRL) ⁽¹⁾
Watchdog timers
Emulation
Hard reset resets everything except for test, emulation logic, and reset isolation modules.
This reset is different from power-on reset in that the PLL Controller assumes power and
clocks are stable when a hard reset is asserted. The device configurations pins are not
relatched.
Emulation-initiated reset is always a hard reset.
By default, these initiators are configured as hard reset, but can be configured (except
emulation) as a soft reset in the RSCFG Register of the PLL Controller. Contents of the
DDR3 SDRAM memory can be retained during a hard reset if the SDRAM is placed in self-
refresh mode.
Soft reset
RESET pin
PLLCTL Register
(RSCTRL)
Watchdog timers
Soft reset behaves like hard reset except that PCIe MMRs (memory-mapped registers) and
DDR3 EMIF MMRs contents are retained.
By default, these initiators are configured as hard reset, but can be configured as soft reset
in the RSCFG Register of the PLL Controller. Contents of the DDR3 SDRAM memory can
be retained during a soft reset if the SDRAM is placed in self-refresh mode.
Local reset
LRESET pin
Watchdog timer timeout
LPSC MMRs
Resets the C66x CorePac, without disturbing clock alignment or memory contents. The
device configuration pins are not relatched.
(1) All masters in the device have access to the PLL Control Registers.
11.4.1 Power-on Reset
Power-on reset is used to reset the entire device, including the test and emulation logic.
Power-on reset is initiated by the following:
1. POR pin
2. RESETFULL pin
230 TCI6630K2L Peripheral Information and Electrical Specifications
Copyright © 2013–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TCI6630K2L