TCI6630K2L Datasheet, PDF (274/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
11.21 Rake Search Accelerator (RSA)
There are eight Rake Search Accelerators (RSAs) on the device. Each C66x CorePac has one set of
directly-connected RSA pairs. The RSA is an extension of the C66x CorePac. The C66x CorePac
performs send/receive to the RSAs via the .L and .S functional units.
11.22 Enhanced Viterbi-Decoder Coprocessor (VCP2)
The device has four high-performance embedded Viterbi Decoder Coprocessors (VCP2) that improve
channel-decoding operations on-chip. Operating at SYSCLK1 clock divided by 3, each VCP2 can decode
more than 762 12.2-Kbps 3G adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels when running at
333 MHz. The VCP2 supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5,
and flexible polynomials, while generating hard decisions or soft decisions. Communications between the
VCP2 and the C66x CorePac are carried out through the EDMA3 controller. The VCP2 supports:
• Unlimited frame sizes
• Code rates 3/4, 1/2, 1/3, 1/4, and 1/5
• Constraint lengths 5, 6, 7, 8, and 9
• Programmable encoder polynomials
• Programmable reliability and convergence lengths
• Hard and soft decoded decisions
• Tail and convergent modes
• Yamamoto logic
• Tail biting logic
• Various input and output FIFO lengths
For more information, see the KeyStone Architecture Viterbi Coprocessor (VCP2) User's Guide
(SPRUGV6).
11.23 Turbo Decoder Coprocessor (TCP3d)
The TCI6630K2L has two high-performance embedded Turbo-Decoder Coprocessors (TCP3d) that speed
up channel-decoding operations on-chip for WCDMA, HSPA, HSPA+, TD-SCDMA, LTE, and WiMAX.
Operating at SYSCLK1 divided by 2 or 3, the TCP3d processes data channels at a throughput
of > 100 Mbps. For more information, see the KeyStone Architecture Turbo Decoder Coprocessor 3
(TCP3d) User's Guide (SPRUGS0).
11.24 Turbo Encoder Coprocessor (TCP3e)
The TCI6630K2L has a high-performance Turbo-Encoder Coprocessor (TCP3e) (embedded in the BCP)
that speeds up channel-encoding operations on-chip for WCDMA, HSPA, HSPA+, TD-SCDMA, LTE, and
WiMAX. Operating at SYSCLK1 divided by 3, the TCP3e is capable of processing data channels at a
throughput of > 200 Mbps. For more information, see the KeyStone Architecture Turbo Encoder
Coprocessor 3 (TCP3e) User's Guide (SPRUGS1).
11.25 Bit Rate Coprocessor (BCP)
BCP is a hardware accelerator for wireless infrastructure and performs most of the uplink and downlink
layer 1 bit processing for 3G and 4G wireless standards. BCP supports LTE, LTE-A, FDD WCDMA, TD-
SCDMA, and WiMAX 802.16-2009 standards. It supports various downlink processing blocks like CRC
attachment, turbo encoding, rate matching, code block concatenation, scrambling, and modulation. BCP
supports various uplink processing blocks like soft slicer, de-scrambler, de-concatenation, rate de-
matching, and LLR combining. For more information, see the KeyStone Architecture Bit Rate Coprocessor
(BCP) User's Guide (SPRUGZ1).
274 TCI6630K2L Peripheral Information and Electrical Specifications
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