TCI6630K2L Datasheet, PDF (210/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
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Bit
21
20-19
18
17
16
15
14-12
11-7
6-0
Table 9-69. USB_PHY_CTL4 Register Field Descriptions (continued)
Field
PHY_RETENABLEN
Description
Lowered Digital Supply Indicator.
PHY_REFCLKSEL
Indicates that the vp digital power supply has been lowered in Suspend mode. This signal
must be de-asserted before the digital power supply is lowered.
• 1 = Normal operating mode.
• 0 = The analog blocks are powered down.
Reference Clock Select for PLL Block.
PHY_COMMONONN
Selects reference clock source for the HS PLL block.
• 11 = HS PLL uses EXTREFCLK as reference.
• 10 = HS PLL uses either ref_pad_clk_{p,m} or ref_alt_clk_{p,m} as reference.
• x0 = Reserved.
Common Block Power-Down Control.
Reserved
PHY_OTG_VBUSVLDEXTSEL
Controls the power-down signals in the HS Bias and PLL blocks when the USB3.0 PHY is in
Suspend or Sleep mode.
• 1 = In Suspend or Sleep mode, the HS Bias and PLL blocks are powered down.
• 0 = In Suspend or Sleep mode, the HS Bias and PLL blocks remain powered and continue
to draw current.
Reserved
External VBUS Valid Select.
PHY_OTG_OTGDISABLE
Selects the VBUSVLDEXT input or the internal Session Valid comparator to indicate when the
VBUS signal on the USB cable is valid.
• 1 = VBUSVLDEXT input is used.
• 0 = Internal Session Valid comparator is used.
OTG Block Disable.
PHY_PC_TX_VBOOST_LVL
Powers down the OTG block, which disables the VBUS Valid and Session End comparators.
The Session Valid comparator (the output of which is used to enable the pull-up resistor on DP
in Device mode) is always on irrespective of the state of otgdisable. If the application does not
use the OTG function, setting this signal to high to save power.
• 1 = OTG block is powered down.
• 0 = OTG block is powered up.
Tx Voltage Boost Level.
PHY_PC_LANE0_TX_TERM_
OFFSET
Reserved
Sets the boosted transmit launch amplitude (mV_ppd).
The default setting is intended to set the launch amplitude to approximately 1,008mV_ppd.
• +1 = results in a +156 mV_ppd change in the Tx launch amplitude.
• -1 = results in a -156 mV_ppd change in the Tx launch amplitude.
Transmitter Termination Offset.
Enables adjusting the transmitter termination value from the default value of 60 Ω.
Reserved
Figure 9-55. USB_PHY_CTL5 Register
31
21
20
Reserved
PHY_REF_CLKDIV2
R-0
R/W-0
12
4
3
PHY_SSC_REF_CLK_SEL
Reserved
R/W-000000000
R-0
Legend: R = Read only; R/W = Read/Write, -n = value after reset
19
13
PHY_MPLL_MULTIPLIER[6:0]
R/W +0011001
2
0
PHY_SSC_RANGE
R/W-000
210 Device Boot and Configuration
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