TCI6630K2L Datasheet, PDF (279/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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PHYSYNC
11
10
TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
RADSYNC
Figure 11-62. AIF Physical Layer Synchronization Pulse Timing
13
12
Figure 11-63. AIF Radio Synchronization Pulse Timing
Table 11-66. AIF Timer Module Switching Characteristics
(see Figure 11-64)
NO.
PARAMETER
MIN
External Frame Event
14 tw(EXTFRAMEEVENTH) Pulse width, EXTFRAMEEVENT output high
8 * C1 ⁽¹⁾
15 tw(EXTFRAMEEVENTL) Pulse width, EXTFRAMEEVENT output low
8 * C1
(1) C1 = 245.76MHz clock for CPRI and 307.2MHz clock for OBSAI.
MAX UNIT
ns
ns
EXT FRAME EVENT
14
15
Figure 11-64. AIF Timer External Frame Event Timing
11.29 Digital Front End (DFE)
The TCI6630K2L integrates the Digital Front-End (DFE) subsystem with Digital Down/Up-Conversion
(DDC/DUC), Crest Factor Reduction (CFR), and Digital Pre-Distortion (DPD) functionality. The DFE
subsystem provides a direct interface to RF analog front-end of the base station.
• Support for up to 4 TX and 4 RX antenna streams. This could be used with DPD to support:
– Up to 50MHz signal BW for 2TX2RX (up to 65MHz with lower DPD performance)
– Up to 25MHz signal BW for 4TX4RX (up to 30MHz with lower DPD performance)
• Support up to 4 lane JESD204A/B (7.37Gbps line rate max) interface to multiple data-converters
• DFE max. clock frequency of 368.64MHz
• Back-end Automatic Gain Control (AGC) supported for WCDMA
• Power measurement supported for LTE
• 8-bit DVGA interface (pin muxed with DFE GPIO)
• 16 DFE GPIOs to interface to Digital Variable Gain Amplifiers (DVGA), RF muxes, Power amplifier
(PA) Time Division Duplex (TDD) controls. These GPIOs are different from the chip-level GPIOs. The
DFE GPIOs are controlled directly by the DFE MMRs.
• DUC/DDC, CFR, DPD, RX integrated
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TCI6630K2L Peripheral Information and Electrical Specifications 279
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