TCI6630K2L Datasheet, PDF (196/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
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Figure 9-34. Timer Input Selection Register (TINPSEL3) for Timer 12-Timer15
31
30
28
Reserved
TINPHSEL15
R-0
RW-0
23
22
20
Reserved
TINPHSEL14
R-0
RW-0
15
14
12
Reserved
TINPHSEL13
R-0
RW-0
7
6
4
Reserved
TINPHSEL12
R-0
RW-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
27
Reserved
R-0
19
Reserved
R-0
11
Reserved
R-0
3
Reserved
R-0
26
24
TINPLSEL15
RW-0
18
16
TINPLSEL14
RW-0
10
8
TINPLSEL13
RW-0
2
0
TINPLSEL12
RW-0
Figure 9-35. Timer Input Selection Register (TINPSEL4) for Timer 16-Timer17
31
Reserved
R-0
15
14
12
11
Reserved
TINPHSEL17
Reserved
R-0
RW-0
R-0
7
6
4
3
Reserved
TINPHSEL16
Reserved
R-0
RW-0
R-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
16
10
8
TINPLSEL17
RW-0
2
0
TINPLSEL16
RW-0
Bit
31-15
11
7
3
14-12
6-4
10-8
2-0
Field
Reserved
TINPHSELx5
TINPLSELx5
Table 9-47. Timer Input Selection Field Description
Description
Input select for TIMER16 high and TIMER17 high.
Input select for TIMER16 low and TIMER17 low.
9.2.3.20 Timer Output Selection Register (TOUTPSELx)
The control register TOUTSELx handles the timer output selection and is shown in Figure 9-36 and
Figure 9-37 and described in Table 9-48.
Figure 9-36. Timer Output Selection 0 Register (TOUTPSEL0)
31
30 29
24 23
22 21
16 15
14 13
87
65
0
Reserved
TOUTPSEL3
Reserved
TOUTPSEL2
Reserved
TOUTPSEL1
Reserved
TOUTPSEL0
R-0
RW-010001
R-0
RW-010000
R-0
RW-010101
R-0
RW-010100
Legend: R = Read only; RW = Read/Write; -n = value after reset
196 Device Boot and Configuration
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