TCI6630K2L Datasheet, PDF (259/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

www.ti.com
TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
11.9 External Interrupts
11.9.1 External Interrupts Electrical Data/Timing
Table 11-46. NMI and LRESET Timing Requirements⁽¹⁾
(see Figure 11-43)
NO.
1 tsu( LRESET - LRESETNMIEN ) Setup time - LRESET valid before LRESETNMIEN low
1 tsu( NMI - LRESETNMIEN )
Setup time - NMI valid before LRESETNMIEN low
1 tsu(CORESELn- LRESETNMIEN ) Setup time - CORESEL[2:0] valid before LRESETNMIEN low
2 th( LRESETNMIEN - LRESET ) Hold time - LRESET valid after LRESETNMIEN high
2 th( LRESETNMIEN - NMI )
Hold time - NMI valid after LRESETNMIEN high
2 th( LRESETNMIEN -CORESELn) Hold time - CORESEL[2:0] valid after LRESETNMIEN high
3 tw( LRESETNMIEN )
Pulsewidth - LRESETNMIEN low width
(1) P = 1/SYSCLK1 clock frequency in ns.
MIN
12*P
12*P
12*P
12*P
12*P
12*P
12*P
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
CORESEL[2:0]/
LRESET/
NMI
LRESETNMIEN
1
2
3
Figure 11-43. NMI and LRESET Timing
11.10 On-Chip Standalone RAM (OSR)
The 1MB OSR is added to the device for:
• QM External Linking RAM
• NetCP1.5 intermediate data buffer
• Intermediate buffering of other data storage
The OSR supported features include:
• SRAM supports ECC with Read-Modify-Write logic
• RTA memory
• Support interrupt for ECC error event
• Support Little and Big-endian modes of operation
OSR does not support any type of cache access, hence this memory space must always be marked as
non-cacheable region for both DSP and ARM cores.
11.11 DDR3A Memory Controller
The 72-bit DDR3 Memory Controller bus of the TCI6630K2L is used to interface to JEDEC standard-
compliant DDR3 SDRAM devices. The DDR3 external bus interfaces only to DDR3 SDRAM devices and
does not share the bus with any other type of peripheral.
11.11.1 DDR3 Memory Controller Device-Specific Information
The TCI6630K2L includes one 64-bit wide, 1.5-V DDR3 SDRAM EMIF interface. The DDR3 interface can
operate at 800 mega transfers per second (MTS), 1033 MTS, 1333 MTS, and 1600 MTS.
Copyright © 2013–2015, Texas Instruments Incorporated
TCI6630K2L Peripheral Information and Electrical Specifications 259
Submit Documentation Feedback
Product Folder Links: TCI6630K2L