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| TCI6630K2L Datasheet, PDF (281/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip | |||
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TCI6630K2L
SPRS893E â MAY 2013 â REVISED JANUARY 2015
11.35 EMIF16 Peripheral
The EMIF16 module provides an interface between the device and external memories such as NAND and
NOR flash. For more information, see the KeyStone Architecture External Memory Interface (EMIF16)
User's Guide (SPRUGZ3).
11.35.1 EMIF16 Electrical Data/Timing
Table 11-67. EMIF16 Asynchronous Memory Timing Requirements(1)
(see Figure 11-65 through Figure 11-68)
NO.
MIN
MAX
UNIT
General Timing
2
tw(WAIT)
Pulse duration, WAIT assertion and deassertion minimum time
28 td(WAIT-WEH) Setup time, WAIT asserted before WE high
14 td(WAIT-OEH) Setup time, WAIT asserted before OE high
Read Timing
2E ns
4E + 3 ns
4E + 3 ns
3
tC(CEL)
EMIF read cycle time when ew = 0, meaning not in extended wait (RS+RST+RH+3) (RS+RST+RH+3) ns
mode
*E-3
*E+3
3
tC(CEL)
EMIF read cycle time when ew =1, meaning extended wait mode (RS+RST+RH+3) (RS+RST+RH+3) ns
enabled
*E-3
*E+3
4
tosu(CEL-OEL)
Output setup time from CE low to OE low. SS = 0, not in select
strobe mode
(RS+1) * E - 3 (RS+1) * E + 3 ns
5
toh(OEH-CEH)
Output hold time from OE high to CE high. SS = 0, not in select
strobe mode
(RH+1) * E - 3 (RH+1) * E + 3 ns
4
tosu(CEL-OEL)
Output setup time from CE low to OE low in select strobe mode,
SS = 1
(RS+1) * E - 3 (RS+1) * E + 3 ns
5
toh(OEH-CEH)
Output hold time from OE high to CE high in select strobe mode,
SS = 1
(RH+1) * E - 3 (RH+1) * E + 3 ns
6
tosu(BAV-OEL) Output setup time from BA valid to OE low
7
toh(OEH-BAIV) Output hold time from OE high to BA invalid
8
tosu(AV-OEL) Output setup time from A valid to OE low
9
toh(OEH-AIV) Output hold time from OE high to A invalid
10 tw(OEL)
OE active time low, when ew = 0. Extended wait mode is
disabled.
(RS+1) * E - 3 (RS+1) * E + 3 ns
(RH+1) * E - 3 (RH+1) * E + 3 ns
(RS+1) * E - 3 (RS+1) * E + 3 ns
(RH+1) * E - 3 (RH+1) * E + 3 ns
(RST+1) * E - 3 (RST+1) * E + 3 ns
10 tw(OEL)
OE active time low, when ew = 1. Extended wait mode is enabled. (RST+1) * E - 3 (RST+1) * E + 3 ns
11 td(WAITH-OEH) Delay time from WAIT deasserted to OE# high
4E + 3 ns
12 tsu(D-OEH)
Input setup time from D valid to OE high
3
ns
13 th(OEH-D)
Input hold time from OE high to D invalid
0.5
ns
Write Timing
15 tc(CEL)
EMIF write cycle time when ew = 0, meaning not in extended wait (WS+WST+WH+ (WS+WST+WH+ ns
mode
TA+4)*E-3
TA+4)*E+3
15 tc(CEL)
EMIF write cycle time when ew =1., meaning extended wait mode (WS+WST+WH+ (WS+WST+WH+ ns
is enabled
TA+4)*E-3
TA+4)*E+3
16
tosuCEL-WEL)
Output setup time from CE low to WE low. SS = 0, not in select
strobe mode
(WS+1) * E - 3
ns
17
toh(WEH-CEH)
Output hold time from WE high to CE high. SS = 0, not in select
strobe mode
(WH+1) * E - 3
ns
16
tosuCEL-WEL)
Output setup time from CE low to WE low in select strobe mode,
SS = 1
(WS+1) * E - 3
ns
17
toh(WEH-CEH)
Output hold time from WE high to CE high in select strobe mode,
SS = 1
(WH+1) * E - 3
ns
18 tosu(RNW-WEL) Output setup time from RNW valid to WE low
19 toh(WEH-RNW) Output hold time from WE high to RNW invalid
20 tosu(BAV-WEL) Output setup time from BA valid to WE low
(WS+1) * E - 3
ns
(WH+1) * E - 3
ns
(WS+1) * E - 3
ns
(1) E = 1/(SYSCLK1/6)
Copyright © 2013â2015, Texas Instruments Incorporated
TCI6630K2L Peripheral Information and Electrical Specifications 281
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