TCI6630K2L Datasheet, PDF (170/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
BYTE
OFFSET
32
34
36
38
40
42
44
46
48
50
52
54
56
58
64
66
70
72
Table 9-16. Ethernet Boot Parameter Table (continued)
NAME
Multi MAC Med
Multi MAC Low
Source Port
Dest Port
Device ID 12
Device ID 34
Dest MAC High
Dest MAC Med
Dest MAC Low
Lane Enable
SGMII Config
SGMII Control
SGMII Adv Ability
Reserved
Eth Ref, High
Eth Ref, Low
PKT PLL Cfg MSW
PKT PLL CFG LSW
DESCRIPTION
CONFIGURED
THROUGH BOOT
CONFIGURATION PINS
The 16 middle bits of the multi-cast MAC address to receive during NO
boot
The 16 LSBs of the multi-cast MAC address to receive during boot NO
The source UDP port to accept boot packets from. A value of 0 will NO
accept packets from any UDP port
The destination port to accept boot packets on.
NO
The first two bytes of the device ID. This is typically a string value, NO
and is sent in the Ethernet ready frame
The 2nd two bytes of the device ID.
NO
The 16 MSBs of the MAC destination address used for the Ethernet NO
ready frame. Default is broadcast.
The 16 middle bits of the MAC destination address
NO
The 16 LSBs of the MAC destination address
NO
One bit per lane.
• 0 - Lane disabled
• 1 - Lane enabled
Bits 0-3 are the config index, bit 4 set if direct config used, bit 5 set if NO
no configuration done
The SGMII control register value
NO
The SGMII ADV Ability register value
NO
SGMII reference clock frequency, MHz. Only 12500 and 15625 are NO
supported.
NO
The packet subsystem PLL configuration, MSW
NO
The packet subsystem PLL configuration, LSW
NO
9.1.2.4.3 PCIe Boot Parameter Table
Table 9-17. PCIe Boot Parameter Table
BYTE
OFFSET
22
NAME
Options
24
Address Width
26
Link Rate
DESCRIPTION
Bits 00 Mode
• 0 = Host Mode (Direct boot mode)
• 1 = Boot Table Boot Mode
Bits 01 Configuration of PCIe
• 0 = PCIe is configured by RBL
• 1 = PCIe is not configured by RBL
Bit 03-02 Reserved
Bits 04 Multiplier
• 0 = SERDES PLL configuration is done based on SERDES
register values
• 1 = SERDES PLL configuration based on the reference clock
values
Bits 05 - 15 = Reserved
PCI address width, can be 32 or 64
SerDes frequency, in Mbps. Can be 2500 or 5000
CONFIGURED
THROUGH BOOT
CONFIGURATION PINS
NO
YES with in conjunction
with BAR sizes
NO
170 Device Boot and Configuration
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