TCI6630K2L Datasheet, PDF (14/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
L1D Mode Bits
000
001
010
011
100
L1D Memory
Block Base
Address
00F0 0000h
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All
SRAM
7/8
SRAM
3/4
SRAM
1/2
SRAM
2-Way
Cache
2-Way
Cache
2-Way
Cache
2-Way
Cache
16K bytes
8K bytes
4K bytes
4K bytes
Figure 4-3. L1D Memory Configurations
00F0 4000h
00F0 6000h
00F0 7000h
00F0 8000h
4.1.3 L2 Memory
The L2 memory configuration for the TCI6630K2L device is as follows:
• Total memory size is 4096KB
• Each CorePac contains 1024KB of memory
• Local starting address for each CorePac is 0080 0000h
L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The
amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2
Configuration Register (L2CFG) of the C66x CorePac. Figure 4-4 shows the available SRAM/cache
configurations for L2. By default, L2 is configured as all SRAM after device reset.
14
C66x CorePac
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