TCI6630K2L Datasheet, PDF (165/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

www.ti.com
TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Table 9-9. NAND Boot Device Configuration Field Descriptions (continued)
Bit
11-9
8
Field
ARM PLL Setting
Boot Master
7-5
SYS PLL Setting
4
Min
3-1
Boot Devices
0
Lendian
Description
ARM PLL Setting. The PLL default settings are determined by the [11:9] bits. This will set the PLL to the
maximum clock setting for the device. Table 9-23 shows settings for various input clock frequencies.
Boot Master select
• 0 = ARM is boot master (default)
• 1 = C66x is boot master
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock
setting for the device. Table 9-23 shows settings for various input clock frequencies.
Minimum boot pin select. When Min is 1, it means that the BOOTMODE [15:3] pins are don't cares. Only
BOOTMODE [2:0] pins (DEVSTAT[3:1]) will determine boot. Default values are assigned to values that
would normally be set by the other BOOTMODE pins when Min is 0.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
Boot Devices
• 011 = NAND boot mode
• Others = Other boot modes
Endianess
• 0 = Big endian
• 1 = Little endian
Copyright © 2013–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TCI6630K2L
Device Boot and Configuration 165