TCI6630K2L Datasheet, PDF (222/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
11.2.1.3 Prolonged Resets
Holding the device in POR, RESETFULL, or RESET for long periods of time may affect the long-term
reliability of the part (due to an elevated voltage condition that can stress the part). The device should not
be held in a reset for times exceeding one hour at a time and no more than 5% of the total lifetime for
which the device is powered-up. Exceeding these limits will cause a gradual reduction in the reliability of
the part. This can be avoided by allowing the device to boot and then configuring it to enter a hibernation
state soon after power is applied. This will satisfy the reset requirement while limiting the power
consumption of the device.
11.2.1.4 Clocking During Power Sequencing
Some of the clock inputs are required to be present for the device to initialize correctly, but behavior of
many of the clocks is contingent on the state of the boot configuration pins. Table 11-4 describes the clock
sequencing and the conditions that affect clock operation. Note that all clock drivers should be in a high-
impedance state until CVDD is at a valid level and that all clock inputs be either active or in a static state
with one leg pulled to ground and the other connected to CVDD.
Table 11-4. Clock Sequencing
CLOCK
SYSCLK
CONDITION
CORECLKSEL[1:0] = 01
or 10
CORECLKSEL[1:0] = 00
CORECLKSEL[1:0] = 00
or 10
ALTCORECLK
CORECLKSEL[1:0] = 01
DDR3ACLK
CORECLKSEL[1:0] = 00
or 01
CORECLKSEL[1:0] = 10
SEQUENCING
SYSCLK is not used and should be tied to a static state.
SYSCLK is used to clock the core PLL. It must be present 16 µsec before POR transitions
high.
ALTCORECLK is not used and should be tied to a static state.
ALTCORECLK is used to clock the core PLL. It must be present 16 µsec before POR
transitions high.
DDR3ACLK is not used.
DDR3ACLK is used to clock the core PLL. It must be present 16 µsec before POR transitions
high.
11.2.2 Power-Down Sequence
The power down sequence is the exact reverse of the power-up sequence described above. The goal is to
prevent an excessive amount of static current and to prevent overstress of the device. A power-good
circuit that monitors all the supplies for the device should be used in all designs. If a catastrophic power
supply failure occurs on any voltage rail, POR should transition to low to prevent over-current conditions
that could possibly impact device reliability.
A system power monitoring solution is needed to shut down power to the board if a power supply fails.
Long-term exposure to an environment in which one of the power supply voltages is no longer present will
affect the reliability of the device. Holding the device in reset is not an acceptable solution because
prolonged periods of time with an active reset can affect long term reliability.
11.2.3 Power Supply Decoupling and Bulk Capacitor
To properly decouple the supply planes on the PCB from system noise, decoupling and bulk capacitors
are required. Bulk capacitors are used to minimize the effects of low-frequency current transients and
decoupling or bypass capacitors are used to minimize higher frequency noise. For recommendations on
selection of power supply decoupling and bulk capacitors see the Hardware Design Guide for KeyStone II
Devices application report (SPRABV0).
222 TCI6630K2L Peripheral Information and Electrical Specifications
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