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| TCI6630K2L Datasheet, PDF (264/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip | |||
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TCI6630K2L
SPRS893E â MAY 2013 â REVISED JANUARY 2015
www.ti.com
11
SDA
8
SCL
4
10
1
3
6
5
12
7
3
2
9
14
13
Stop Start
Repeated
Start
Stop
Figure 11-45. I2C Receive Timings
Table 11-49. I2C Switching Characteristics(1)
(see Figure 11-46)
STANDARD
MODE
FAST MODE
NO.
PARAMETER
MIN
MAX
MIN MAX UNIT
16
tc(SCL)
Cycle time, SCL
10
17
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low (for a repeated START
condition)
4.7
2.5
µs
0.6
µs
18
th(SDAL-SCLL)
Hold time, SDA low after SCL low (for a START and a repeated
START condition)
4
0.6
µs
19
tw(SCLL)
Pulse duration, SCL low
20
tw(SCLH)
Pulse duration, SCL high
21 td(SDAV-SDLH) Delay time, SDA valid to SCL high
22 tv(SDLL-SDAV) Valid time, SDA valid after SCL low (for I2C bus devices)
23
tw(SDAH)
Pulse duration, SDA high between STOP and START
conditions
24
tr(SDA)
Rise time, SDA
25
tr(SCL)
Rise time, SCL
26
tf(SDA)
Fall time, SDA
27
tf(SCL)
Fall time, SCL
28 td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition)
Cp
Capacitance for each I2C pin
4.7
1.3
µs
4
0.6
µs
250
100
ns
0
0
0.9 µs
4.7
1.3
µs
1000
1000
300
300
20 + 0.1Cb(1)
20 + 0.1Cb(1)
20 + 0.1Cb(1)
20 + 0.1Cb(1)
300 ns
300 ns
300 ns
300 ns
4
0.6
µs
10
10 pF
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
264 TCI6630K2L Peripheral Information and Electrical Specifications
Copyright © 2013â2015, Texas Instruments Incorporated
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Product Folder Links: TCI6630K2L
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