TCI6630K2L Datasheet, PDF (265/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
SDA
SCL
26
23
19
25
16
18
21
20
27
22
18
17
24
28
Stop
Start
Repeated
Start
Stop
Figure 11-46. I²C Transmit Timings
11.13 SPI Peripheral
The Serial Peripheral Interconnect (SPI) module provides an interface between the SoC and other SPI-
compliant devices. The primary intent of this interface is to allow for connection to an SPI ROM for boot.
The SPI module on TCI6630K2L is supported only in master mode. Additional chip-level components can
also be included, such as temperature sensors or an I/O expander.
11.13.1 SPI Electrical Data/Timing
(see Figure 11-47)
NO.
7 tsu(SPIDIN-SPC)
7 tsu(SPIDIN-SPC)
7 tsu(SPIDIN-SPC)
7 tsu(SPIDIN-SPC)
8 th(SPC-SPIDIN)
8 th(SPC-SPIDIN)
8 th(SPC-SPIDIN)
8 th(SPC-SPIDIN)
Table 11-50. SPI Timing Requirements
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 0
Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 1
Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 0
Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 1
Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 0
Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 1
Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 0
Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 1
MIN MAX UNIT
2
ns
2
ns
2
ns
2
ns
5
ns
5
ns
5
ns
5
ns
Table 11-51. SPI Switching Characteristics
(see Figure 11-47 and Figure 11-48)
NO.
PARAMETER
MIN
1
tc(SPC)
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
Cycle time, SPICLK, all master modes
3*P2 ⁽¹⁾
2
tw(SPCH)
Pulse width high, SPICLK, all master modes
0.5*(3*P2) - 1
3
tw(SPCL)
Pulse width low, SPICLK, all master modes
0.5*(3*P2) - 1
4
td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge
on SPICLK. Polarity = 0, Phase = 0.
4
td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge
on SPICLK. Polarity = 0, Phase = 1.
4
td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge
on SPICLK Polarity = 1, Phase = 0
MAX UNIT
ns
ns
ns
5 ^ns
5 ^ns
5 ^ns
(1) P2=1/(SYSCLK1/6)
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TCI6630K2L Peripheral Information and Electrical Specifications 265
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