TCI6630K2L Datasheet, PDF (175/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
NOTE
Other frequencies are support but require a boot in a pre-configured mode.
The configuration for the PASS PLL is also shown. The PASS PLL is configured with these values only if
the Ethernet boot mode is selected with the input clock set to match the main PLL clock (not the SGMII
SerDes clock). See Table 9-10 for details on configuring Ethernet boot mode. The output from the PASS
PLL goes through an on-chip divider to reduce the frequency before reaching the NETCP. The PASS PLL
generates 1050 MHz, and after the chip divider (/3), applies 350 MHz to the NETCP.
The Main PLL is controlled using a PLL controller and a chip-level MMR. The DDR3A PLL and NETCP
PLL are controlled by chip level MMRs. For details on how to set up the PLL see Section 11.5. For details
on the operation of the PLL controller module, see the KeyStone Architecture Phase Locked Loop (PLL)
Controller User's Guide (SPRUGV2).
Table 9-23. System PLL Configuration
INPUT
800 MHz DEVICE
BOOTMODE CLOCK
[7:5]
FREQ (MHz) PLLD PLLM DSP ƒ
1000 MHz DEVICE
PLLD PLLM DSP ƒ
1200 MHz Device
PLLD PLLM DSP ƒ
NETCP = 350 MHz ⁽¹⁾
PLLD PLLM ^{DSP ƒ (2)}
0b000
50.00
0
31
800
0
39
1000 0
47
1200 0
41
1050
0b001
66.67
0
23
800.04 0
29
1000.05 0
35
1200.06 1
62
1050.053
0b010
80.00
0
19
800
0
24
1000 0
29
1200 3
104 1050
0b011
100.00
0
15
800
0
19
1000 0
23
1200 0
20
1050
0b100
156.25
3
40
800.78 4
63
1000 2
45
1197.92 24
335 1050
0b101
250.00
4
31
800
0
7
1000 4
47
1200 4
41
1050
0b110
312.50
7
40
800.78 4
31
1000 2
22
1197.92 24
167 1050
0b111
122.88
0
12
798.72 3
64
999.989 0
19
1228.80 11
204 1049.6
(1) The PASS PLL generates 1050 MHz and is internally divided by 3 to feed 350 MHz to the packet accelerator.
(2) ƒ represents frequency in MHz.
9.1.4.1 ARM CorePac System PLL Settings
The PLL default settings are determined by the BOOTMODE[11:9] bits. Table 9-24 shows settings for
various input clock frequencies. This will set the PLL to the maximum clock setting for the device.
CLK = CLKIN × ((PLLM+1) ÷ ((OUTPUT_DIVIDE+1) × (PLLD+1)))
Where OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]
The ARM CorePac PLL is controlled using a PLL controller and a chip-level MMR. For details on how to
set up the PLL see Section 11.5. For details on the operation of the PLL controller module, see the
KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide (SPRUGV2).
BOOTMODE
[11:9]
0b000
0b001
0b010
0b011
0b100
0b101
0b110
0b111
INPUT CLOCK
FREQ (MHz)
50.00
66.67
80.00
100.00
156.25
250.00
312.50
122.88
Table 9-24. ARM PLL Configuration
800 MHz DEVICE
PLLD PLLM ARM ƒ
0
31
800
0
23
800.04
0
19
800
0
15
800
0
40
800.78
4
31
800
7
40
800.78
0
12
798.72
1000 MHz DEVICE
PLLD PLLM ARM ƒ
0
39
1000
0
29
1000.05
0
24
1000
0
19
1000
4
63
1000
0
7
1000
4
31
1000
3
64
999.40
1200 MHz DEVICE
PLLD PLLM DSP ƒ
0
47
1200
0
35
1200.06
0
29
1200
0
23
1200
24
45
1197.92
4
47
1200
2
22
1197.92
0
19
1228.80
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