TCI6630K2L Datasheet, PDF (182/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
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9.2.3.2 Device Configuration Register
The Device Configuration Register is one-time writeable through software. The register is reset on all hard
resets and is locked after the first write. The Device Configuration Register is shown in Figure 9-12 and
described in Table 9-28.
Figure 9-12. Device Configuration Register (DEVCFG)
31
Reserved
R-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
5
4
3
2
1
0
PCIESS_1_
MODE
PCIESS_0_
MODE
SYSCLKOUT
EN
R/W-00
R/W-00
R/W-1
Table 9-28. Device Configuration Register Field Descriptions
Bit
31-5
4-3
2-1
0
Field
Reserved
PCIESS_1_MODE
PCIESS_0_MODE
SYSCLKOUTEN
Description
Reserved. Read only, writes have no effect.
Device Type Input of PCIeSS_1
• 00 = Endpoint
• 01 = Legacy Endpoint
• 10 = Rootcomplex
• 11 = Reserved
Device Type Input of PCIeSS_0
• 00 = Endpoint
• 01 = Legacy Endpoint
• 10 = Rootcomplex
• 11 = Reserved
SYSCLKOUT enable
• 0 = No clock output
• 1 = Clock output enabled (default)
9.2.3.3 Pin Mux Control Register
Pin mux control registers are used to control the various pins that are muxed at the chip level.
9.2.3.3.1 Pin Mux Control 0 Register (PIN_MUXCTL0)
The Pin Mux Control 0 Register is shown in Figure 9-13 and described in Table 9-29.
Figure 9-13. Pin Mux Control 0 Register (PIN_MUXCTL0)
31
87
65
4
3
Reserved UART3_EMIFA_SEL UART2_EMIFA_SEL Reserved
R-0
R/W-0
R/W-00
R, 0
Legend: R = Read only; RW = Read/Write; -n = value after reset
2
UART01_SPI2_
SEL
R/W-0
1
DFESYNC_RP1_
SEL
R/W-0
0
AVSIF_SEL
R/W-0
Table 9-29. Pin Mux Control 0 Register Field Descriptions
Bit
31-8
7-6
Field
Reserved
UART3_EMIFA_SEL
Description
Reserved. Read only, writes have no effect.
• 00 - Select EMIF A22- A23, CE2-CE3 (Default)
• 01 - Select UART3 without flow control (RXD, TXD only) and EMIF CE2 - CE3
• 10 - Reserved
• 11 - Select UART3 with flow control
182 Device Boot and Configuration
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