TCI6630K2L Datasheet, PDF (189/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Bit
Field
31 GR
30-4 Reserved
3 LR3
2 LR2
1 LR1
0 LR0
Table 9-35. Reset Status Register Field Descriptions
Description
Global reset status
• 0 = Device has not received a global reset.
• 1 = Device received a global reset.
Reserved.
C66x CorePac3 reset status
• 0 = C66x CorePac3 has not received a local reset.
• 1 = C66x CorePac3 received a local reset.
C66x CorePac2 reset status
• 0 = C66x CorePac2 has not received a local reset.
• 1 = C66x CorePac2 received a local reset.
C66x CorePac1 reset status
• 0 = C66x CorePac1 has not received a local reset.
• 1 = C66x CorePac1 received a local reset.
C66x CorePac0 reset status
• 0 = C66x CorePac0 has not received a local reset.
• 1 = C66x CorePac0 received a local reset.
9.2.3.9 Reset Status Clear (RESET_STAT_CLR) Register
The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR
register. The Reset Status Clear Register is shown in the figure and table below.
Figure 9-20. Reset Status Clear Register (RESET_STAT_CLR)
31 30
GR
R-1
Legend: R = Read only; -n = value after reset
Reserved
R- 0
4
3
2
1
0
LR3
LR2
LR1
LR0
R-0
R-0
R-0
R-0
Bit Field
31
GR
30-4 Reserved
3
LR3
2
LR2
1
LR1
0
LR0
Table 9-36. Reset Status Clear Register Field Descriptions
Description
Global reset clear bit
• 0 = Writing a 0 has no effect.
• 1 = Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register.
Reserved.
C66x CorePac3 reset clear bit
• 0 = Writing a 0 has no effect.
• 1 = Writing a 1 to the LR3 bit clears the corresponding bit in the RESET_STAT register.
C66x CorePac2 reset clear bit
• 0 = Writing a 0 has no effect.
• 1 = Writing a 1 to the LR2 bit clears the corresponding bit in the RESET_STAT register.
C66x CorePac1 reset clear bit
• 0 = Writing a 0 has no effect.
• 1 = Writing a 1 to the LR1 bit clears the corresponding bit in the RESET_STAT register.
C66x CorePac0 reset clear bit
• 0 = Writing a 0 has no effect.
• 1 = Writing a 1 to the LR0 bit clears the corresponding bit in the RESET_STAT register.
9.2.3.10 Boot Complete (BOOTCOMPLETE) Register
The BOOTCOMPLETE register controls the BOOTCOMPLETE pin status to indicate the completion of the
ROM booting process. The Boot Complete register is shown in the figure and table below.
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Device Boot and Configuration 189