TCI6630K2L Datasheet, PDF (289/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
ARM and DSP simultaneous trace is not supported.
11.37.2 Master ID for HW and SW Messages
Table 11-70 describes the master ID for the various hardware and software masters of the STM.
Table 11-70. MSTID Mapping for Hardware Instrumentation (CPTRACERS)
MSTID [7:0]
0x94-0x97
0xB1
0xAE - 0xB0
0x98
0x8C - 0x93
0xA4
0xA5
0xA6
0x99
0x9A
0xA0
0x9B
0xA7
0x9C
CPTRACER NAME
CPT_MSMCx_MST, where x =
0..3
CPT_MSMC4_MST
CPT_MSMCx_MST, where x =
5..7
CPT_DDR3A_MST
CPT_L2_x_MST, where x = 0..3
CPT_TPCC0_4_MST
CPT_TPCC1_2_3_MST
CPT_INTC_MST
CPT_SM_MST
CPT_QM_CFG1_MST
CPT_QM_CFG2_MST
CPT_QM_M_MST
CPT_SPI_ROM_EMIF16_MST
CPT_CFG_MST
0x9D
0x9E
0x9F
CPT_RAC_FEI_MST
CPT_RAC_CFG1_MST
CPT_TAC_BE_MST
CLOCK
DOMAIN
SYSCLK1/1
SYSCLK1/1
SYSCLK1/1
SYSCLK1/1
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SID[4:0]
0x0..3
DESCRIPTION
MSMC SRAM Bank 0 to MSMC SRAM Bank 3 monitors
0x4
0x5..7
MSMC SRAM Bank 4
MSMC SRAM Bank 5to MSMC SRAM Bank 7 monitors
0x8
0x9..0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
MSMC DDR3A port monitor
DSP 0 to 3 SDMA port monitors
EDMA 0 CFG port monitor
EDMA 1and EDMA2 CFG port monitor
INTC port monitor (for INTC 0/1 and GIC400)
Semaphore CFG port monitors
QMSS CFG1 port monitor
QMSS CFG2 port monitor
QM_M CFG/DMA port monitor
SPI ROM EMIF16 CFG port monitor
SCR_3P_B and SCR_6P_B CFG peripheral port
monitors
RAC_FE port monitor
RAC A CFG port monitor
TAC_BE port monitor
MSTID [7:0]
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0x46
Table 11-71. MSTID Mapping for Software Messages
CORE NAME
C66x CorePac0
C66x CorePac1
C66x CorePac2
C66x CorePac3
Reserved
Reserved
Reserved
Reserved
A15 Core0
A15 Core1
Reserved
Reserved
QMSS PDSPs
DESCRIPTION
C66x CorePac MDMA Master ID
C66x CorePac MDMA Master ID
C66x CorePac MDMA Master ID
C66x CorePac MDMA Master ID
ARM Master IDs
ARM Master ID
All QMSS PDSPs share the same master ID. Differentiating between the 8 PDSPs is done
through the channel number used
11.37.3 SoC Cross-Triggering Connection
The cross-trigger lines are shared by all the subsystems implementing cross-triggering. An MPU
subsystem trigger event can therefore be propagated to any application subsystem or system trace
component. The remote subsystem or system trace component can be programmed to be sensitive to the
global SOC trigger lines to either:
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TCI6630K2L Peripheral Information and Electrical Specifications 289
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