TCI6630K2L Datasheet, PDF (181/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
9.2.3.1 Device Status (DEVSTAT) Register
The Device Status Register depicts device configuration selected upon a power-on reset by the POR or
RESETFULL pin. Once set, these bits remain set until a power-on reset. The Device Status Register is
shown in the figure below.
Figure 9-11. Device Status Register
31
29
28
27
26
25
Reserved
CSISC2_3_MUXSEL CSISC2_0_CLKCTL CSISC2_0_MUXSEL
DDR3A_MAP_EN
R-0
R-x
R-x
R-1
R-1
24
20
19
18
17
16
1
0
Reserved
R-x
MAINPLLODSEL
R/W-x
AVSIFSEL
R/W-x
BOOTMODE
R/W-x xxxx xxxx xxxx
xxx
LENDIAN
R-x ⁽¹⁾
Legend: R = Read only; RW = Read/Write; -n = value after reset
(1) x indicates the bootstrap value latched via the external pin
Table 9-27. Device Status Register Field Descriptions
Bit
31-29
28
27
26
25
24-20
19
18-17
16-1
0
Field
Reserved
CSISC2_3_MUXSEL
CSISC2_0_CLKCTL
CSISC2_0_MUXSEL
DDR3A_MAP_EN
Reserved
MAINPLLODSEL
AVSIFSEL
BOOTMODE
LENDIAN
Description
Reserved. Read only, writes have no effect.
SerDes Mux selection between SGMII and PCIe0/1.
• 0 = CSIS2_3 is assigned to SGMII (lane 2 and 3).
• 1 = CSIS2_3 is assigned to PCIe_0 lane 0 and PCIe_1 lane 0.
SerDes reference clock selection
• 0 = CSIS2_0 and CSIS2_1 use separate SerDes reference clocks. CSIS2_0_REFCLK drives CSIS2_0
and CSIS2_1_REFCLK drives CSIS2_1.
• 1 = CSIS2_0 and CSIS2_1 share a single common SerDes reference clock (default)
CSIS2_0_REFCLK drives both CSIS2_0 and CSIS2_1.
SerDes Mux selection between JESD and AIL.
• 0 = CSIS2_0 is assigned to JESD (lane 0 and 1).
• 1 = CSIS2_0 is assigned to AIL (lane 0 and 1).
DDR3A mapping enable
• 0 = Reserved
• 1 = DDR3A memory is accessible in 32b space from ARM, i.e., at 0x0:8000_0000 - 0x0:FFFF_FFFF.
DDR3A is also accessible at 0x8:0000_0000 - 0x9:FFFF_FFFF, with the space 0x0:8000_0000 -
0x0:FFFF_FFFF address aliased at 0x8:0000_0000 - 0x8:7FFF_FFFF.
Reserved
Main PLL Output divider select
• 0 = Main PLL output divider needs to be set to 2 by BOOTROM (default)
• 1 = Reserved
AVS interface selection
• 00 - AVS 4pin 6bit Dual-Phase VCNTL[5:2] (Default)
• 01 - AVS 4pin 4bit Single-Phase VCNTL[5:2]
• 10 - AVS 6pin 6bit Single-Phase VCNTL[5:0]
• 11 - I²C
Determines the bootmode configured for the device. For more information on bootmode, see Section 9.1.2
and see the KeyStone II Architecture ARM Bootloader User's Guide (SPRUHJ3).
Device endian mode (LENDIAN) — shows the status of whether the system is operating in big endian
mode or little endian mode (default).
• 0 = System is operating in big endian mode
• 1 = System is operating in little endian mode (default)
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Device Boot and Configuration 181