TCI6630K2L Datasheet, PDF (17/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
4.3 Bandwidth Management
When multiple requestors contend for a single C66x CorePac resource, the conflict is resolved by granting
access to the highest priority requestor. The following four resources are managed by the bandwidth
management control hardware:
• Level 1 Program (L1P) SRAM/Cache
• Level 1 Data (L1D) SRAM/Cache
• Level 2 (L2) SRAM/Cache
• Memory-mapped registers configuration bus
The priority level for operations initiated within the C66x CorePac are declared through registers in the
CorePac. These operations are:
• DSP-initiated transfers
• User-programmed cache coherency operations
• IDMA-initiated transfers
The priority level for operations initiated outside the CorePac by system peripherals is declared through
the Priority Allocation Register (PRI_ALLOC). System peripherals with no fields in PRI_ALLOC have their
own registers to program their priorities.
More information on the bandwidth management features of the CorePac can be found in
theTMS320C66x DSP CorePac User's Guide (SPRUGW0).
4.4 Power-Down Control
The C66x CorePac supports the ability to power-down various parts of the CorePac. The power-down
controller (PDC) of the CorePac can be used to power down L1P, the cache control hardware, the DSP,
and the entire CorePac. These power-down features can be used to design systems for lower overall
system power requirements.
NOTE
The TCI6630K2L does not support power-down modes for the L2 memory at this time.
More information on the power-down features of the C66x CorePac can be found in the TMS320C66x
DSP CorePac User's Guide (SPRUGW0).
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