TCI6630K2L Datasheet, PDF (251/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
11.6 DDR3A PLL
The DDR3A PLL generates interface clocks for the DDR3A memory controller. When coming out of
power-on reset, DDR3A PLL is programmed to a valid frequency during the boot configuration process
before being enabled and used.
DDR3A PLL power is supplied via the DDR3 PLL power-supply pin (AVDDA6-AVDDA10). An external EMI
filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone II Devices
application report (SPRABV0) for detailed recommendations.
PLLM
DDR3 PLL
DDR3CLK(N|P)
PLLD
VCO
0
CLKOD
1
DDR3
PLLOUT
DDR3
PHY
INTBYPASS
Figure 11-28. DDR3A PLL Block Diagram
11.6.1 DDR3A PLL Control Registers
The DDR3A PLL, which is used to drive the DDR3A PHY for the EMIF, does not use a PLL controller.
DDR3A PLL can be controlled using the DDR3APLLCTL0 and DDR3APLLCTL1 registers located in the
Bootcfg module. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to
these registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers.
For suggested configurable values, see Section 9.1.4.1. See Section 9.2.3.5 for the address location of
the registers and locking and unlocking sequences for accessing the registers. These registers are reset
on POR only.
Figure 11-29. DDR3A PLL Control Register 0 (DDR3APLLCTL0)
31
24
23
22
19
18
6
BWADJ[7:0]
BYPASS
CLKOD
PLLM
RW,+0000 1001
RW,+0
RW,+0001
RW,+0000000010011
Legend: RW = Read/Write; -n = value after reset
5
0
PLLD
RW,+000000
Bit Field
31-24 BWADJ[7:0]
23
BYPASS
22-19 CLKOD
18-6 PLLM
5-0 PLLD
Table 11-31. DDR3A PLL Control Register 0 Field Descriptions
Description
BWADJ[11:8] and BWADJ[7:0] are located in DDR3APLLCTL0 and DDR3APLLCTL1 registers. BWADJ[11:0]
should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
Enable bypass mode
• 0 = Bypass disabled
• 1 = Bypass enabled
A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values
from 2 to 16. CLKOD field is loaded with output divide value minus 1
A 13-bit field that selects the values for the PLL multiplication factor. PLLM field is loaded with the multiply
factor minus 1
A 6-bit field that selects the values for the reference (input) divider. PLLD field is loaded with reference divide
value minus 1
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TCI6630K2L Peripheral Information and Electrical Specifications 251
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