TCI6630K2L Datasheet, PDF (156/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
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The Packet DMA secondary port is one master port that does not have priority allocation register inside
the Multicore Navigator. The priority level for transaction from this master port is described by the
QM_PRIORITY bit field in the CHIP_MISC_CTL0 register shown in Figure 9-45 and Table 9-60.
For all other modules, see the respective User's Guides listed in Section 3.5 for programmable priority
registers.
156 System Interconnect
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