TCI6630K2L Datasheet, PDF (168/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
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9.1.2.3.2 UART Boot Device Configuration
Figure 9-10. UART Boot Mode Configuration Field Description
16 15 14 13 12
X X X X Port
DEVSTAT Boot Mode Pins ROM Mapping
11
10 9
8
7
6
5
ARM PLL Cfg
Boot Master
Sys PLL Config
4 321
0
Min
111
Lendian
Bit
16-13
12
Field
Reserved
Port
11-9
8
ARM PLL
Setting
Boot Master
7-5 SYS PLL
Setting
4
Min
3-1 Boot Devices
0
Lendian
Table 9-13. UART Boot Configuration Field Descriptions
Description
Not Used
UART Port number
• 0 = UART0 (default)
• 1 = UART1
The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for
the device. Table 9-23 shows settings for various input clock frequencies.
Boot Master select
• 0 = ARM is boot master
• 1 = C66x is boot master
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for
the device. Table 9-23 shows settings for various input clock frequencies. (default = 4)
Minimum boot configuration select bit.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table
for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
Boot Devices[3:1]
• 111 = UART boot mode
• Others = Other boot modes
Endianess
• 0 = Big endian
• 1 = Little endian
9.1.2.4 Boot Parameter Table
The ROM Bootloader (RBL) uses a set of tables to carry out the boot process. The boot parameter table is
the most common format the RBL employs to determine the boot flow. These boot parameter tables have
certain parameters common across all the boot modes, while the rest of the parameters are unique to the
boot modes. The common entries in the boot parameter table are shown in Table 9-14.
BYTE OFFSET
0
2
4
6
8
10
12
14
16
18
Table 9-14. Boot Parameter Table Common Parameters
NAME
Length
Checksum
Boot Mode
Port Num
SW PLL, MSW
SW PLL, LSW
Sec PLL Config, MSW
Sec PLL Config, LSW
System Freq
Core Freq
DESCRIPTION
The length of the table, including the length field, in bytes.
The 16 bits ones complement of the ones complement of the entire table. A
value of 0 will disable checksum verification of the table by the boot ROM.
Internal values used by RBL for different boot modes.
Identifies the device port number to boot from, if applicable
PLL configuration, MSW
PLL configuration, LSW
ARM PLL configuration, MSW
ARM PLL configuration, LSW
The Frequency of the system clock in MHz
The frequency of the core clock in MHz
168 Device Boot and Configuration
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