TCI6630K2L Datasheet, PDF (232/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
chip contention during the warm reset, all I/O must be Hi-Z for modules affected by RESET.
2. Once all logic is reset, RESETSTAT is asserted (driven low) to denote that the device is in reset.
3. The RESET pin can now be released. A minimal device initialization begins to occur. Note that
configuration pins are not re-latched and clocking is unaffected within the device.
4. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).
NOTE
The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise,
if POR is activated (brought low), the minimum POR pulse width must be met. The RESET
pin should not be tied to the POR pin.
11.4.3 Soft Reset
A soft reset behaves like a hard reset except that the EMIF16 MMRs, DDR3A EMIF MMRs, PCIe MMRs
sticky bits, and external memory content are retained. POR should also remain de-asserted during this
time.
Soft reset is initiated by the following:
• RESET pin
• RSCTRL Register in the PLL Controller
• Watchdog timer
In the case of a soft reset, the clock logic and the power control logic of the peripherals are not affected
and, therefore, the enabled/disabled state of the peripherals is not affected. On a soft reset, the DDR3A
memory controller registers are not reset. If the user places the DDR3A SDRAM in self-refresh mode
before invoking the soft reset, the DDR3A SDRAM memory content is retained.
During a soft reset, the following occurs:
1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset propagates
through the system. Internal system clocks are not affected. PLLs remain locked.
2. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the
PLL Controller pauses system clocks for approximately 8 cycles. At this point:
– The peripherals remain in the state they were in before the soft reset.
– The states of the Boot Mode configuration pins are preserved as controlled by the DEVSTAT
Register.
– The DDR3A MMRs and PCIe MMRs retain their previous values. Only the DDR3A memory
controller and PCIe state machines are reset by the soft reset.
– The PLL Controller remains in the mode it was in prior to the soft reset.
– System clocks are unaffected.
The boot sequence is started after the system clocks are restarted. Because the Boot Mode configuration
pins are not latched with a soft reset, the previous values (as shown in the DEVSTAT Register), are used
to select the boot mode.
11.4.4 Local Reset
The local reset can be used to reset a particular C66x CorePac without resetting any other device
components.
Local reset is initiated by the following:
• LRESET pin
232 TCI6630K2L Peripheral Information and Electrical Specifications
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