TCI6630K2L Datasheet, PDF (270/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
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11.17 Security Accelerator
The Security Accelerator (SA) provides wire-speed processing on 1 Gbps Ethernet traffic on IPSec, SRTP,
and 3GPP Air interface security protocols. It functions on the packet level with the packet and the
associated security context being one of the above three types. The Security Accelerator is coupled with
the Network Coprocessor, and receives the packet descriptor containing the security context in the buffer
descriptor and the data to be encrypted/decrypted in the linked buffer descriptor. For more information,
see the KeyStone II Architecture Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide
(SPRUHZ1).
11.18 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem
The gigabit Ethernet (GbE) switch subsystem provides an efficient interface between the device and the
networked community. The Ethernet Media Access Controller (EMAC) supports 10Base-T
(10 Mbits/second), and 100BaseTX (100 Mbps), in half- or full-duplex mode, and 1000BaseT (1000 Mbps)
in full-duplex mode, with hardware flow control and quality-of-service (QOS) support. The GbE switch
subsystem is coupled with the Network Coprocessor. For more information, see the Gigabit Ethernet
(GbE) Switch Subsystem (1 GB) User's Guide (SPRUGV9).
An address range is assigned to the TCI6630K2L. Each individual device has a 48-bit MAC address and
consumes only one unique MAC address out of the range. There are two registers to hold these values,
MACID1[31:0] (32 bits) and MACID2[15:0] (16 bits) . The bits of these registers are defined as follows:
Figure 11-53. MACID1 Register (MMR Address 0x02620110)
31
0
MACID
R,+xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Legend: R = Read only; -x, value is indeterminate
Bit
31-0
Field
MAC ID
Table 11-54. MACID1 Register Field Descriptions
Description
MAC ID. Lower 32 bits.
Figure 11-54. MACID2 Register (MMR Address 0x02620114)
31
24
23
CRC
R+,cccc cccc
LEGEND: R = Read only; -x = value is indeterminate
Reserved
R,+rr rrrr
18
17
FLOW
R,+z
16
BCAST
R,+y
15
0
MACID
R,+xxxx xxxx xxxx xxxx
Bit
31-24
23-18
17
Field
Reserved
Reserved
FLOW
16
BCAST
15-0 MAC ID
Table 11-55. MACID2 Register Field Descriptions
Description
Variable
000000
MAC Flow Control
• 0 = Off
• 1 = On
Default m/b-cast reception
• 0 = Broadcast
• 1 = Disabled
MAC ID. Upper 16 bits.
270 TCI6630K2L Peripheral Information and Electrical Specifications
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