TCI6630K2L Datasheet, PDF (294/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
11.37.7.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the TCI6630K2L device includes an internal pulldown (IPD) on the TRST pin to
ensure that TRST will always be asserted upon power up and the device’s internal emulation logic will
always be properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments
actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high, but
expect the use of an external pullup resistor on TRST. When using this type of JTAG controller, assert
TRST to initialize the device after powerup and externally drive TRST high before attempting any
emulation or boundary scan operations.
11.37.7.2 JTAG Electrical Data/Timing
Table 11-78. JTAG Test Port Timing Requirements
(see Figure 11-70)
NO.
MIN
1
t_c(TCK)
Cycle time, TCK
23
1a tw(TCKH)
Pulse duration, TCK high (40% of tc)
9.2
1b tw(TCKL)
Pulse duration, TCK low(40% of tc)
9.2
3 tsu(TDI-TCK) Input setup time, TDI valid to TCK high
2
3 tsu(TMS-TCK) Input setup time, TMS valid to TCK high
2
4 th(TCK-TDI)
Input hold time, TDI valid from TCK high
10
4 th(TCK-TMS) Input hold time, TMS valid from TCK high
10
MAX UNIT
ns
ns
ns
ns
ns
ns
ns
(see Figure 11-70)
NO.
2
t_d(TCKL-TDOV)
Table 11-79. JTAG Test Port Switching Characteristics
PARAMETER
MIN
Delay time, TCK low to TDO valid
MAX UNIT
8.24 ns
TCK
TDO
3
TDI / TMS
1
1a
1b
2
4
Figure 11-70. JTAG Test-Port Timing
294 TCI6630K2L Peripheral Information and Electrical Specifications
Copyright © 2013–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TCI6630K2L