TCI6630K2L Datasheet, PDF (277/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
11.27 Semaphore2
The device contains an enhanced Semaphore module for the management of shared resources of the
SoC. The Semaphore enforces atomic accesses to shared chip-level resources so that the read-modify-
write sequence is not broken. The Semaphore module has unique interrupts to each of the CorePacs to
identify when that CorePac has acquired the resource.
Semaphore resources within the module are not tied to specific hardware resources. It is a software
requirement to allocate semaphore resources to the hardware resource(s) to be arbitrated.
The Semaphore module supports three masters and contains 64 semaphores that can be shared within
the system.
There are two methods of accessing a semaphore resource:
• Direct Access: A CorePac directly accesses a semaphore resource. If free, the semaphore is granted.
If not free, the semaphore is not granted.
• Indirect Access: A CorePac indirectly accesses a semaphore resource by writing to it. Once the
resource is free, an interrupt notifies the CorePac that the resource is available.
11.28 IQNet (IQN)
The TCI6630K2L has the new IQNet IP. The IQN subsystem interfaces external I/O into TI DMA
systems.The IQN subsystem consists of the AID module (Antenna interface for DFE), AIL module, AIF
timer (AT) module, one PKTDMA interface, DIO engine and IQ streaming switch (IQS).
• Transport of baseband antenna streams over AIL physical links
• Transport of baseband antenna streams to an integrated Digital Front-End (DFE) IP via AID block
• Support the following radio standards transport: WCDMA, LTE, TD-SCDMA on OBSAI, CPRI/ORI
• Support at least two simultaneous radio standards from the following: WCDMA, LTE, WiMax,
GSM/Edge/EGPRS, TD-SCDMA
• Support a minimum of 16 Ingress + 16 Egress WCDMA channels.
• Support a minimum of 8 Ingress + 8 Egress LTE20 channels.
• Support up to 2 AIL lanes
– AIL supports OBSAI RP3 or CPRI5.0 at 9.83 Gbps line rate max
– AIL supports following OBSAI link rates - 2x, 4x and 8x
– AIL supports following CPRI link rates - 2x, 4x, 5x, 8x, 10x and 16x
– Allows link-to-link forwarding as defined in OBSAI/CPRI
– Support AIL PHY reset isolation
• Integrated AIF2 Timer (AT)
– 24 System Events, 1 BCN counter, 8 complex RADT (radio timers)
– Supports various timing sync sources - RP1, generic input pins, CPTS or software
For more information, see the KeyStone II Architecture IQN2 User's Guide (SPRUH06).
Table 11-65. AIF Timer Module Timing Requirements
(see Figure 11-60, Figure 11-61, Figure 11-62, and Figure 11-63)
NO.
RP1 Clock and Frameburst
1 tc(RP1CLKN)
Cycle time, RP1CLK(N)
1 tc(RP1CLKP)
Cycle time, RP1CLK(P)
2 tw(RP1CLKNL)
Pulse duration, RP1CLK(N) low
3 tw(RP1CLKNH)
Pulse duration, RP1CLK(N) high
3 tw(RP1CLKPL)
Pulse duration, RP1CLK(P) low
2 tw(RP1CLKPH)
Pulse duration, RP1CLK(P) high
MIN
MAX UNIT
32.55
32.55
ns
32.55
32.55
ns
0.4 * C1⁽¹⁾
0.6 * C1
ns
0.4 * C1 0.6 * C1
ns
0.4 * C1 0.6 * C1
ns
0.4 * C1 0.6 * C1
ns
(1) C1 = tc(RP1CLKN/P)
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