TCI6630K2L Datasheet, PDF (174/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
BYTE
OFFSET
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
88
92
96
100
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120 - 376
Table 9-22. DDR3 Boot Parameter Table (continued)
NAME
pllPostDiv
sdRamConfig
sdRamConfig2
sdRamRefreshctl
sdRamTiming1
sdRamTiming2
sdRamTiming3
IpDfrNvmTiming
powerMngCtl
iODFTTestLogic
performcountCfg
performCountMstRegSel
readIdleCtl
sysVbusmIntEnSet
sdRamOutImpdedCalcfg
tempAlertCfg
ddrPhyCtl1
ddrPhyCtl2
proClassSvceMap
mstId2ClsSvce1Map
mstId2ClsSvce2Map
eccCtl
eccRange1
eccRange2
rdWrtExcThresh
Chip Config
DESCRIPTION
PLL post divider value (Should be the exact value not value -1)
SDRAM config register
SDRAM Config register
SDRAM Refresh Control Register
SDRAM Timing 1 Register
SDRAM Timing 2 Register
SDRAM Timing 3 Register
LP DDR2 NVM Timing Register
Power management Control Register
IODFT Test Logic Global Control Register
Performance Counter Config Register
Performance Counter Master Region Select Register
Read IDLE counter Register
System Interrupt Enable Set Register
SDRAM Output Impedence Calibration Config Register
Temperature Alert Configuration Register
DDR PHY Control Register 1
DDR PHY Control Register 1
Priority to Class of Service mapping Register
Master ID to Class of Service Mapping 1 Register
Master ID to Class of Service Mapping 2Register
ECC Control Register
ECC Address Range1 Register
ECC Address Range2 Register
Read Write Execution Threshold Register
Chip Specific PHY configuration
CONFIGURED
THROUGH BOOT
CONFIGURATION PINS
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
9.1.2.5 Second-Level Bootloaders
Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader
allows for:
• Any level of customization to current boot methods
• Definition of a completely customized boot
9.1.3 SoC Security
The TI SoC contains security architecture that allows the C66x CorePacs and ARM CorePac to perform
secure accesses within the device. For more information, contact a TI sales office for additional
information available with the purchase of a secure device.
9.1.4 System PLL Settings
The PLL default settings are determined by the BOOTMODE[7:5] bits. Table 9-23 shows the settings for
various input clock frequencies. This will set the PLL to the maximum clock setting for the device.
CLK = CLKIN × ((PLLM+1) ÷ ((OUTPUT_DIVIDE+1) × (PLLD+1)))
Where OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]
174 Device Boot and Configuration
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