TCI6630K2L Datasheet, PDF (202/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
9.2.3.26 ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
Figure 9-43. ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
31
43
0
Reserved
SIZE
R-0000 0000 0000 0000 0000 0000 0000
RW
Legend: RW = Read/Write; R = Read only
Table 9-56. ARM Endian Configuration Register 1
Default Values
ARM ENDIAN CONFIGURATION REGISTER 1
ARMENDIAN_CFG0_1
ARMENDIAN_CFG1_1
ARMENDIAN_CFG2_1
ARMENDIAN_CFG3_1
ARMENDIAN_CFG4_1
ARMENDIAN_CFG5_1
ARMENDIAN_CFG6_1
ARMENDIAN_CFG7_1
DEFAULT
VALUES
0x00000006
0x00000009
0x00000004
0x00000008
0x00000005
0x0000000A
0x00000000
0x00000000
Bit
31-4
3-0
Field
Reserved
SIZE
Table 9-57. ARM Endian Configuration Register 1 Field Descriptions
Description
Reserved
4-bit encoded size of Configuration Region R
The value in the SIZE field defines the size of the contiguous block of Memory Mapped Register space for
which a word swap is done by the ARM CorePac bridge (starting from ARMENDIAN_CFGr_0.BASEADDR).
• 0000 : 64KB
• 0001 : 128KB
• 0010 : 256KB
• 0011 : 512KB
• 0100 : 1MB
• 0101 : 2MB
• 0110 : 4MB
• 0111 : 8MB
• 1000 : 16MB
• 1001 : 32MB
• 1010 : 64MB
• 1011 : 128MB
• Others : Reserved
9.2.3.27 ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7
The registers defined in ARM Configuration Register 2 (ARMENDIAN_CFGr_2) enable the word swapping
of a region.
Figure 9-44. ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7
31
Legend: RW = Read/Write
Reserved
R-0000 0000 0000 0000 0000 0000 0000 000
1
0
DIS
RW-0
202 Device Boot and Configuration
Submit Documentation Feedback
Product Folder Links: TCI6630K2L
Copyright © 2013–2015, Texas Instruments Incorporated