TCI6630K2L Datasheet, PDF (234/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
POR
1
RESETFULL
RESET
RESETSTAT
3
Figure 11-4. RESETFULL Reset Timing
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POR
RESETFULL
2
RESET
4
RESETSTAT
Figure 11-5. Soft/Hard Reset Timing
Table 11-12. Boot Configuration Timing Requirements⁽¹⁾
(see Figure 11-6)
NO.
MIN
1 tsu(GPIOn-RESETFULL) Setup time - GPIO valid before RESETFULL asserted
12C
2 th(RESETFULL-GPIOn) Hold time - GPIO valid after RESETFULL asserted
12C
(1) C = 1/SYSCLK1 clock frequency in ns.
POR
1
RESETFULL
MAX
UNIT
ns
ns
GPIO[15:0]
2
Figure 11-6. Boot Configuration Timing
11.5 PLLs
This section provides a description of the Main PLL, ARM PLL, DDR3A PLL, NETCP PLL, DFE PLL and
the PLL Controller (Figure 11-7).
234 TCI6630K2L Peripheral Information and Electrical Specifications
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