TCI6630K2L Datasheet, PDF (254/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
www.ti.com
Table 11-34. NETCP PLL Control Register 0 Field Descriptions (NETCPPLLCTL0) (continued)
Bit
18-6
Field
PLLM
5-0 PLLD
Description
A 13-bit field that selects the values for the multiplication factor. PLLM field is loaded with the multiply factor
minus 1.
A 6-bit field that selects the values for the reference divider. PLLD field is loaded with reference divide value
minus 1.
Figure 11-34. NETCP PLL Control Register 1 (NETCPPLLCTL1)
31
15
14
13
Reserved
PLLRST
NETCPPLL
RW - 00000000000000000
RW-0
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
12
7
Reserved
RW-000000
6
ENSAT
RW-0
5
4
Reserved
R-00
3
0
BWADJ[11:8]
RW-0000
Table 11-35. NETCP PLL Control Register 1 Field Descriptions (NETCPPLLCTL1)
Bit
31-15
14
Field
Reserved
PLLRST
13
NETCPPLL
12-7
6
5-4
3-0
Reserved
ENSAT
Reserved
BWADJ[11:8]
Description
Reserved
PLL Reset bit
• 0 = PLL Reset is released
• 1 = PLL Reset is asserted
• 0 = Not supported
• 1 = NETCPPLL
Reserved
Needs to be set to 1 for proper PLL operation
Reserved
BWADJ[11:8] and BWADJ[7:0] are located in NETCPPLLCTL0 and NETCPPLLCTL1 registers. BWADJ[11:0]
should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
11.7.3 NETCP PLL Device-Specific Information
As shown in Figure 11-32, the output of NETCP PLL (PLLOUT) is divided by 3 and directly fed to the
Network Coprocessor. During power-on resets, the internal clocks of the NETCP PLL are affected as
described in Section 11.4. The NETCP PLL is unlocked only during the power-up sequence and is locked
by the time the RESETSTAT pin goes high. It does not lose lock during any other resets.
11.8 DFE PLL
The DFE PLL generates interface clocks for the DFE and IQNet peripherals. When coming out of power-
on reset, DFE PLL comes out in a bypass mode and needs to be programmed to a valid frequency before
being enabled and used.
DFE PLL power is supplied via the DFE PLL power-supply pins (AVDDA1-AVDDA5). An external EMI
filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone II Devices
application report (SPRABV0) for detailed recommendations.
254 TCI6630K2L Peripheral Information and Electrical Specifications
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