TCI6630K2L Datasheet, PDF (235/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
DFE
PLL
DFE PLLOUT
DDR3
PLL
DDR3 PLLOUT
ARM
PLL
ARM PLLOUT
SYSCLK(N|P)
DDR3CLK
ALTCORECLK(N|P)
CORECLKSEL[1:0]
NETCP
PLL
Main
PLL
PLL
Controller
NETCP PLLOUT
MAIN PLLOUT
SYSCLK1-4
Figure 11-7. K2L PLLs
The ARM PLL, DDR3A PLL NETCP PLL, and DFE PLL are used to provide dedicated clock to the ARM
CorePac, DDR3A, NETCP and DFE respectively. These chip level PLLs support a wide range of multiplier
and divider values, which can be programmed through the chip level registers located in the Device
Control Register block. The Boot ROM will program the multiplier values for main PLL, ARM PLL, NETCP
PLL and DFE PLL based on boot mode. (See Section 9 for more details.)
11.5.1 Main PLL and PLL Controller
The Main PLL is controlled by the standard PLL Controller. The PLL Controller manages the clock ratios,
alignment, and gating for the system clocks to the device. By default, the device powers up with the main
PLL bypassed. Figure 11-8 shows a block diagram of the Main PLL and the PLL Controller. For details on
the operation of the PLL Controller module, see the KeyStone Architecture Phase Locked Loop (PLL)
Controller User's Guide (SPRUGV2).
The DDR3A PLL is used to supply clock to DDR3A EMIF logic. This PLL can also be used without
programming the PLL Controller. Instead, they can be controlled using the chip-level registers
(DDR3APLLCTL0, DDR3APLLCTL1) located in the Device Control Register block. To write to these
registers, software must go through an unlocking sequence using the KICK0/KICK1 registers.
The multiplier values for all chip-level PLLs can be reprogrammed later based on the input parameter
table. This feature provides flexibility in that these PLLs may be able to reuse other clock sources instead
of having its own clock source.
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TCI6630K2L Peripheral Information and Electrical Specifications 235
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